Paging <Introduction>

1. Paging<Introduction> Bojun Seo(bojun@aces.snu.ac.kr) School of Computer Science and Engineering Seoul National University

2. Contents • Basic concepts of paging • Paging and virtual addressing • Concepts of page table • Role of page table • Organization of PTE(Page table Entry) • Pitfalls of page table • Too big • Too slow • Observation of its working

3. Basic concepts of paging • OS cannot manage memory spaces without splitting • There are two ways to split the spaces(virtual or physical whatever) • Divide the memory space into variable-sized pieces • Divide the memory space into fixed-sized pieces • The latter(fixed-sized) one is paging variable-sized fixed-sized

4. Paging and virtual addressing • Paging divides each spaces(virtual and physical) into same size • One example how virtual address space is mapped on physical address space

5. Concepts of page table • The mapping information that which goes where should be saved • Page table saves that information • Page table entry can be accessed by VPN(Virtual Page Number) • Each entry keeps PFN(Physical Frame Number) • (and some bit information, which will be dealt on later slides)

6. Role of page table • Example, assume page size of previous picture was 16 bytes • Then, Virtual memory space size is 16*4 = 64 bytes • log264 = 6 bits • And Physical memory space size is 16*8 = 128 bytes • log2128 = 7 bits

7. Role of page table • Example, assume page size of previous picture was 16 bytes • Offset bits of physical and virtual memory are exactly same • Translation is not needed • Page table entry doesn’t keep every bits of address

8. Role of page table • Example, assume page size of previous picture was 16 bytes • Translation example

9. Organization of PTE • PTE(Page Table Entry) have PFN and some bits for managing • valid bit: whether translation of this page is valid or not • protection bits: whether this page can be read from, written to, or executed from • present bit: whether this page is on the memory or disk • dirty bit: whether this page has been modified since it was brought into memory • reference bit: used to track whether this page has been accessed, which is useful in determining which pages are popular

10. Organization of PTE PTE of x86 architecture source: https://www.cs.uaf.edu/2007/fall/cs301/lecture/11_30_cache.html retrieved 2015.05.03

11. Pitfalls of paging(Too big) • Calculate the size of page table • Imagine 32-bit address space with 4KB pages • assume 4bytes per PTE • 220 * 4 = 4MB • 4MB memory is needed per process • Imagine we have 100 processes, 400MB of main memory will be occupied by the page tables • Since maximum memory size of 32-bit system is 4GB, 400MB is too big and cannot be acceptable • In case of 64-bit system with 4KB pages • assume 4bytes per PTE • 252 * 4 = 4PB(peta bytes) memory is needed per process

12. Pitfalls of paging(Too slow) • Followings are translation steps • extract VPN from virtual address • calculate PTE address • extract PFN(memory accessing) • concatenate PFN and offset • Translation from virtual address to physical address occurs at every instruction • And translation itself is memory referencing, it’s too slow

13. Observation of its working C code x86 assembly Page table referencing has temporal and spatial locality

14. Summary • Paging is managing memory with splitting memory with fixed-sized pieces • Translating information from virtual address to physical address is saved in page tables • Each process has its own page table • Naive paging has two problems • Too big page tables • Too slow access speed • Page table referencing has temporal and spatial locality • Maybe.. this property is used to solve the problems above