1 / 21

Toward PDN Resource Estimation: A Law of General Power Density

Toward PDN Resource Estimation: A Law of General Power Density. Kwangok Jeong and Andrew B. Kahng ( kjeong@ucsd.edu , abk@ucsd.edu ) VLSI CAD Laboratory University of California San Diego. Outline. Power and technology trend Early stage PDN estimation Power law of power density

wlejeune
Download Presentation

Toward PDN Resource Estimation: A Law of General Power Density

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Toward PDN Resource Estimation: A Law of General Power Density Kwangok Jeong and Andrew B. Kahng (kjeong@ucsd.edu, abk@ucsd.edu) VLSI CAD Laboratory University of California San Diego

  2. Outline • Power and technology trend • Early stage PDN estimation • Power law of power density • Data collection: random activity distribution • Model 1: empirical activity density model • Model 2: analytical power density model • Toward PDN resource estimation • Conclusion

  3. Power and Technology Trends • Power trend and required impedance scaling • Frequency increases • Power increases • Vdd decreases • Current increases • Required impedance decreases ITRS 2010 MPU

  4. Need for Early PDN Estimation and Synthesis • When we have enough information… • Placement information • Power consumption of gates • Stimuli for realistic worst operation • PDN can be designed with detailed information • At the early design stage, when we do not have enough information… • Expected (average/worst) power of a functional block • Rough estimate of area of the functional block • Still need to estimate PDN resources toplan interconnect stack, chip size, bump pitch, etc.considering routing congestion increase due to PDN

  5. PDN Design at the Early Design Stage • Traditional procedure • Decide mesh pitch (and/or width)  Assign current sources  Refine mesh width • Current source distribution • Given a current consumption (Iexpected) • Evenly distributed sources • A single source at center Iexpected / N N: #nodes What is realisticcurrent distribution? Iexpected Too pessimistic! Too optimistic!

  6. Trend of Power Density • Exponential dependency of power density to area • What is the general property of the activity density? 1.4e+3 1.2e+3 1.0e+3 0.8e+3 Current density (A/cm2) 0.6e+3 0.4e+3 AF=7.5% 0.2e+3 0.0e+0 0 5 10 15 20 25 30 35 40 45 50 Device level Block level Chip level unit area count (J)

  7. Activity Density • Activity density = activity count within a window • Correlated with power density • What is the maximum activity density? Die (N x N) Activity density changes with respect to window size and locations Activity density changes with respect to time Sampling window (m x m) Activity at t=T Activity at t=3 Activity at t=2 Activity at t=1

  8. Normalized Maximum Activity Density • Artificial activity distribution • Given NN grids and average activity factor p, • Randomly assign activity 1 to pNN grids out of NN grids • Maximum activity density for m = 1 to N c(m)  maximum #activity enclosed by mm area d(m)  c(m) / m2 for m = 1 to N dnorm(m) d(m) / d(N) • Activity density is not a constant N= 5, p=0.2 c(1) = 1  d(1) = 1.00  dnorm(1) = 5.00 c(2) = 2  d(2) = 0.50  dnorm(2) = 2.50 c(3) = 3  d(3) = 0.33  dnorm(3) = 1.32 c(4) = 4  d(4) = 0.25  dnorm(4) = 1.25 c(5) = 5  d(5) = 0.20  dnorm(5) = 1.00

  9. Normalized Power Density in a Real Design • Testcase: sparc_exu_alu (in OpenSparcT1) • #instance: 3k • Core size: 130um x 130um • Power estimation flow • Synthesis: Synopsys Design Compiler • Place&route: Cadence SoC Encounter • System-level simulation: VirtuTech SIMICS • Gate-level simulation: Cadence NC Verilog • Power estimation: Synopsys PrimeTime-PX • Among 1M cycles, top-1000 high power cycles are collected • Power assignment • Divide core area into 100 x100 grids • Assign the power of each cell to the corresponding grid, based on the cell location Linear in a log-log plot  Existence of power law dnorm(m) m (a) Single cycle dnorm(m) m (b) Multiple cycles (for w-timeframes)

  10. Activity Count Calculation • Massive data collection for activity count statistics using a dynamic programming approach for x = 1 to N for y = 1 to N CA[ x ][ y ][ 1 ] = CountInBox1(x,y) for m = 2 to N for x = 1 to N for y = 1 to N if ( m == even ) lb  CA[ x ][ y ][ m/2 ] lt  CA[ x ][ y+m/2 ][ m/2 ] rb  CA[ x+m/2 ][ y ][ m/2 ] rt  CA[ x+m/2 ][ y+m/2 ][ m/2 ] CA[ x ][ y ][ m ]  lb + lt + rb + rt else lb  CA[ x ][ y ][ m/2 ] lt  CA[ x ][ y+m/2 ][ m/2+1 ] rb  CA[ x+m/2 ][ y ][ m/2+1 ] rt  CA[ x+m/2+1][ y+m/2+1 ][ m/2 ] cn  CA[ x+m/2 ][ y+m/2 ][ 1 ] CA[x][y][m]  lb + lt + rb + rt - cn • Parameters to change: • Switching activity (p): 0.05, 0.10, 0.15, 0.25, 0.50, 0.90 • Trial (k): 50 • #Timeframes (w): 1, 2, 4, 8, 32 • Window size (m): 1, 2, …, 100 m = 3 (x,y) CA[x][y][3] = 1 lt rt rb lb lt rt rb lb cn

  11. Activity Density from Random Distributions • Single timeframe • Multiple timeframes P = 0.05 Normalized activity density: dnorm(m) Log (dnorm(m)) Log (m) Sample window size: m P = 0.90 • Summary of characteristics • Exponential decay with m • m=1 and w = 1  dnorm(w) = 1/p • Large m  dnorm(w) = 1 • Large w  small dnorm(w) • Large p  small impact of w • Small p  large impact of w Log (dnorm(m)) Log (m)

  12. Empirical Activity Density Model • Model function is determined to capture the characteristics of the observed activity density • Model coefficients are found using fitting with measured data • Summary of characteristics • Exponential decay with m • m=1 and w = 1  dnorm(w) = 1/p • Large m  dnorm(w) = 1 • Large w  small dnorm(w) • Large p  small impact of w • Small p  large impact of w For small p (~ 0), impact of w is large, andfor large p (~1), impact of w is small Exponential decay due to m Large m  dnorm(m) = 1 Slow decay due to w m = 1 and w =1  dnorm(m) = 1/p

  13. Model Validation – Empirical Model dnorm(m) • Model accuracy for all data points • Average error: 6.14%, Maximum error: 40.15% dnorm(m) m m dnorm(m) dnorm(m) m dnorm(m) m dnorm(m) m dnorm(m) m m

  14. Analytical Modeling from Chernoff Bound • Fact 1 (Chernoff Bound): • Let x1,…,xn be mutually independent 0/1 random variables, each equal to 1 with probability p. • If for any 0 <  < 1, then • Let sij be a 0/1 random variable denoting activity at (i,j) • We find maximum activity count in rectangles of size m  m whose top-right corner is (u,v) •  (of in Chernoff bound) = pm2 ,

  15. Analytical Activity Count Model • From Chernoff bound, maximum activity count is bounded as: • For a single timeframe: • For a multiple timeframes: with probability at least 1 -  with probability at least 1 - 

  16. Model Validation – Analytical Model • Model • We find model coefficient  for various  values • Validation using all data points used in empirical model construction • For all  values,  is near 1  tight estimate • When cases m < 10 are removed, avg (max) error  3.17%~ 4.88% (23.77%~41.60%)

  17. Preliminary Results for PDN Design • IR-drop comparison for a fixed power mesh • 1mm2 region consuming 100mA • Mesh width = 2um, mesh pitch = 10um • PDN resource comparison for a fixed 5% voltage drop • 1mm2 region consuming 100mA • Mesh pitch: 10um Center Uniform Power law (p=0.001) I = 100mA 100mA (100x100) I = Max drop: 73.0mV Max drop: 31.7mV Max drop: 37.4mV

  18. Conclusions and Ongoing Works • We have presented a general law for power density • We provide closed-form activity density models from empirical data analysis and probability theory • These can be used to improve the accuracy and efficiency of early-stage PDN resource prediction • Our ongoing work • Further simplification of models • Validation against large industry designs • Development of fast and accurate PDN design and optimization methodologies for early stages of IC design

  19. THANK YOU!

  20. BACKUP

  21. Power Estimation Flow power report (dynamic & leakage power) benchmark binary - bzip, equak, ... (SPEC-2000) benchmark analysis SimPoint power estimation PrimeTime-PX reprehensive execution phase switching activity (VCD) wire load (SPEF) system-level simulation Simics + Transplant functional simulation NC-Verilog input patterns (stimuli) gate-level netlist delay info. (SDF) RTL design OpenSPARC T1 design implementation DC, SOCE

More Related