Sandia Petaflops Workshop Overview for SOS7

1. Sandia Petaflops WorkshopOverview for SOS7 Erik P. DeBenedictis Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company,for the United States Department of Energy under contract DE-AC04-94AL85000.

2. Fishing • I was a kid in Alaska during 5th grade • Bought Ted Williams (?) fishing kit for $10 • For a year: threw hook in water, waited 5 minutes and pulled it out • Never caught anything • Conclusion: Fishing mostly an exercise in patience • No fishing for me

3. Objective • What do you put into a supercomputer chip in year 20XX • Consumer microprocessor (Hammer, Power, Intel, …) • PIM • Whose? • FPGA • Why?

4. Domain of Optimization • Sandia/DOE Emphasis on Supercomputer Architecture • Interests • Architectures that run our applications well • Scalability over the long haul – 10 years • Competing approaches • Preserve code base for a particular CPU line (X86) • Repurpose commercial hardware • Peak FLOPS

5. Value Chain TechnologyDiegertDeBenedictis ArchitectureBurgerSterlingTomkins Applications HoisieChristopher Bender Systems Support Maccabe ValueDelivery [via batch] LeungRudolph Tomkins

6. Carl Diegert Physical packaging topic To minimize delay, shrink machine This doesn’t cut power and eventually you reach cooling limits Erik DeBenedictis Technology scaling and “balance factors” topic Moore’s Law permits oracle into the future Project future of balanced supercomputers Talks 1 & 2

7. Generalization of Moore’s Law Projects many parameters Years through 2016 Includes justification Panel of experts known to be wrong Size between Albuquerque white and yellow pages SIA Semiconductor Roadmap

8. Thomas Sterling Gilgamesh/MIND PIM Architecture A physically realizable supercomputer candidate Unconventional programming Doug Burger TRIPS PIM Architecture A physically realizable supercomputer candidate Unconventional programming Talks 3 & 4

9. TRIPS

10. Sense Amps Sense Amps Memory Stack Memory Stack Decode Basic Silicon Macro Sense Amps Sense Amps Node Logic Sense Amps Sense Amps Memory Stack Memory Stack Sense Amps Sense Amps Single Chip Gilgamesh

11. Jim Tomkins Traditional Roadmap of DOE Supercomputer purchases Programmable Physically realizable? Adolfy Hoisie (Giving Kerbyson’s talk, who had family emergency) Estimating performance of key Government applications on machines that have not been build yet Talks 5 & 6

12. Thomas Christopher Fusing Moore’s Law’s clairvoyance with application performance estimation Predict performance of machines based on abstract trends 10 years into the future Barney Maccabe FAST-OS Can we put a runtime system on whatever transpires? Talks 7 & 8

13. Estimating Performance

14. Michael Bender Are there ways we can incrementally change the way we program to meet the limitations of the laws of physics? Vitus Leung Fast programs are only part of the picture: the batch scheduler runs the show Batch schedulers typically waste 15% – 40% of a machine What new issues will peta-scale supercomputers introduce? Talks 9 & 10

15. Larry Rudolph In detail, how do we value a peta-scale supercomputer Peak flops? Throughput? Response time? Talk 11

16. 48 GFLOPS Hammer  20 picoseconds/flop • 2 FLOPS/clock  40 ps clock period • Speed of light = 1 foot/ns • Or .04”/40 ps • On a chip say .5 c • .02” per clock cycle • 50 clock cycles to get across 1” chip • Challenge • Enormous pipelining