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Interconnect-Centric Design for Advanced SoC and NoC

Interconnect-Centric Design for Advanced SoC and NoC. Communication-based Design for Network-on-chip Sun Linghao. Chapter 1: System-on-chip Challenges in the Deep-sub-micron Era. Outline Introduction Challenging the SoC Prospects The Platform Approach to System-on-a-Chip

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Interconnect-Centric Design for Advanced SoC and NoC

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  1. Interconnect-Centric Design for Advanced SoC and NoC Communication-based Design for Network-on-chip Sun Linghao ©TUT 2004

  2. Chapter 1: System-on-chip Challenges in the Deep-sub-micron Era • Outline • Introduction • Challenging the SoC Prospects • The Platform Approach to System-on-a-Chip • Platform-based Design and Networks-on-a-Chip • Summary and Perspectives ©TUT 2004

  3. Introduction • No reason for Moore’s law to a screeching halt! • Scaling of semiconductor creates a true SoC; • i.e. Integration of a complete electronic system including all its periphery and interfaces on a single die. • The enthusiastic embrace of SoC vision has cooled down over last 1-2 years. • Speculated on 90’s and come to full bearing today • Deep-submicron, manufacturing cost, and complexity. • The shift of IC design have marked the end of era of ASIC. • A successful product were brought to market • Using specific integrated circuit, • Design flow combining logic synthesis, • Automatic place and route. ©TUT 2004

  4. Introduction – cont. • In response to these challenges • ”Platform-based design” proposed • Reuse at high levels of granularity • Relying on flexibility and programmability • Amortize the NRE costs. ©TUT 2004

  5. Outline • Introduction • Challenging the SoC Prospects • The Platform Approach to System-on-a-Chip • Platform-based Design and Networks-on-a-Chip • Summary and Perspectives ©TUT 2004

  6. The Demise of ASIC • Number of successful IC starts per year ©TUT 2004

  7. The Demise of ASIC – cont. 1 • Non-Recurring Engineering (NRE) cost of manufacturing • Sub-micron design is approching $1M for the 0.13 CMOS technology node; • predicted to between $2M and $5M in 2 to 3 years from now; • ASIC starts suffer the most from the trend; • Favor approaches where customization achieved by software or configurable hardware (ASSPs) • Cost of mask set versus technology node ©TUT 2004

  8. The Demise of ASIC – cont. 2 • Deep-submicron effects • ASIC designer expose to myriad of problems; • Issues like interconnect delay,crosstalk and supply noise impact the predictability of final design; • EDA vendors are struggling to solve timing closure and capacity issues, in the attempt to extend the life of their tools. • Power dissipation, leakage, and variability compound the problem. • Verification has come to dominate the overall design cost. ©TUT 2004

  9. The Demise of ASIC – cont. 3 • Complexity • Design with more than 100 million transistors are not exceptional anymore; • Complexity increase requires either large design team, or raise the time-to-market; • Aggressive reuse of large modules and raise in abstraction levels can help to address this challenging issues. ©TUT 2004

  10. The SoC challenges of the Next Decade • Managing and Exploiting Flexibility (i.e. Introducing higher levels of abstraction) • Moving towards programmable solutions to save NRE and design costs and reduce time-to-market. • This trend requires software as an essential component. • High level of abstraction consisting of mathematical model of the functions. • This approach goes to the name model-based software design; • Software for timing and power estimation, analysis, synthesis, formal verification are all important components. ©TUT 2004

  11. The SoC challenges of the Next Decade – cont. 1 • Implementation thchniques for a set of functions can be approached with the same method at all levels of abstraction; • Various levels in a seamless environment that is based on the tenet of platform-based design. • Power and Energy • Power and energy management and minimization have been concern in CMOS for over more than a decade. ©TUT 2004

  12. The SoC challenges of the Next Decade – cont. 2 • Power and energy management is emerging as one of the most dominate roadblock because of • Integration complexity; • Side-effects of deep submicron transistor scaling. • New design approaches and accompanying design methodologies are a necessity • Solutions to management of leakage and timing uncertainty for low-voltage design; • Impact to reliability from soft errors and reduced signal-to-noise ratio; • Power and energy management is best addressed as a system-level problem; • ASSPs replace ASICs by speed demands for IC design. ©TUT 2004

  13. The SoC challenges of the Next Decade – cont. 3 • Reliability and Robustness • Variety of factors are conspiring reduce the reliability of integrated systems • Reduce signal-to-noise ratio by power considerations; • Soft errors by voltage scaling inject dynamic errors into computation; • Increased impact of process variations,quantum fluctuations, projected proneness to errors of nano-technologies. • The integration of multiple hybrid and mixed-signal technologies on the same die further reduces the design robustness, but can be addressed by • A layered top-down design as advocated in platform-based design is the only way of dealing with dynamic errors; • Verification and test approaches are on a convergence and substantial fractions turned into online activities. ©TUT 2004

  14. The SoC challenges of the Next Decade – cont. 4 • Predictability and Timing Strategies • Timing predictability will continue to decline over the coming years; • This can be contributed to increased variations in both device characteristics and interconnect parameters; • Uncertainty margin over clock period will increase; • The only solution is to step away from the worst-case (synchronous) design by either: • Allowing occasional timing errors to occur- which trade off reliability; • By stepping away from the synchronous paradigm; • We predict that asynchronous (or other non-synchronous) timing strategies will play an important role. ©TUT 2004

  15. The SoC challenges of the Next Decade – cont. 5 • Real-Time Emulation • A complete portfolio of complementary verification techniques (including simulation,emulation,online checking, as well as formal verification) and an overlaying methodology for their dvelopment is necessary. • System level verification by availibility of complex heterogeneous field programmable devices. • Engine constructed and rapid mapping make real-time emulation of complex systems. • A fast prototyping path can go a long way in aiding the verification task. ©TUT 2004

  16. The SoC challenges of the Next Decade – cont. 6 • Mixed Everything (Mixed-Signal & Mixed-Technology) • Integating multiple hybrid technologies into a single component or package. • Not only digital computational functions • But also periphery and interfaces to the external world. • The tight integration of the components requires a design methodology that considers them in concert. • Mixed-signal, mixed-technology methodologies, re-use strategies and tool-sets are essential components of any SoC development. ©TUT 2004

  17. The SoC challenges of the Next Decade – cont. 7 • Beyond Silicon • New technologies and devices (commonly dubbed nano-technologies) are most likely to come into play • Platform-based design methodology(GSRC), based on a stacked layer of abstractions, is universal and is well-suited to encapsulate late-silicon and nano-technoloy devices and fabrics. * GSRC – Gigascale Systems Research Center ©TUT 2004

  18. Outline • Introduction • Challenging the SoC Prospects • The Platform Approach to System-on-a-Chip • Platform-based Design and Networks-on-a-Chip • Summary and Perspectives ©TUT 2004

  19. Platform Definitions • Platform Definitions • In IC domain, a platform is considered a ”flexible” integrated circuit where customization for a particular application is achieved by ”programming” one or more of the compoments on the chip. • ”Programming” implies: • Metal customization (Gate Arrays); • Electrical modification (FPGA personalization); • Software to run on microprocessor or DSP. ©TUT 2004

  20. Platform Definitions– cont. 1 • For software, ”platform” is designed as fixed micro-architechture to minimuize the costs but flexible enough. e.g. • Micro-controller for automobile from Motorola; • Wireless DSPs such as TI C50. • The problem with this approach is lack of optimization that make performance too low and size too high. • A better approach is to develop ”a family” or similiar chips that differ for one or more but based on the same microprocessor, such as 54 and 55 of TI C50. • The family and its programmatic interface is ”platform”. ©TUT 2004

  21. Platform Definitions– cont. 2 • Again, a platform is a clearly defined articulation point of restriction and abstraction. • E.g. Use of standard cells restrict the design space but high-quality acceptable solutions. • Sychronous timing methodology adds another restriction to design space. • Synchronous standard cell based design as a platform was the key enable of ASIC design methodology. ©TUT 2004

  22. Platform Definitions– cont. 3 • The salient aspects of platform based design should • Meet in the middle approach • Leverages the power of top-down and efficiency of bottom-up; • A stepwise refinement of specification by chosen restricted library and available components; • Once a paticular collection of components of the platform is selected, we obtain a platform instance. • The stepwise refinement continues by defining the selected platform instance as a specification, untill a component is fully instantiated. • The selection of the parameters to use to guide the platform instance selsction is one of the critical parts of platform based design. ©TUT 2004

  23. Platform Definitions– cont. 4 • Component selection process and verification can be carried out automatically by the platform based design. • Platforms form a stack, from design specification to implementation. • Circuit implementation level refines the platform from standard cells to fabrics. • Architecture level shifts from ASIC to ASSP. • System level platforms increases the reuse of components as a way to manage incresing complexity. ©TUT 2004

  24. Some Platform Examples • Some Platform Examples • Platform concept has been particularly successful in thr PC world. • Platform concept in the design of integrated embedded systems. • Nexperia platform – Philips • Ericsson Mobile Platform • TI OMAP architecture platform • VertexPro Silicon Platform - Xilinx ©TUT 2004

  25. Some Platform Examples – cont. 1 • Nexperia platform for multimedia applications • Computational modules can be added or dropped based on application needs; • The core of platform is formed by the communication networks, which consists of this particular case of a set of busses. ©TUT 2004

  26. Outline • Introduction • Challenging the SoC Prospects • The Platform Approach to System-on-a-Chip • Platform-based Design and Networks-on-a-Chip • Summary and Perspectives ©TUT 2004

  27. Network-on-a-Chip Basics • Communication between components requires the definition of protocol. • Traditional on-chip communcaiton design has been done using ad-hoc informal approaches • But it fails to meet some challenges posed by next-generation SoC, such as: • Performance and throughput; • Power and energy; • Reliability and predictability; • Synchronization and managment of concurrency. ©TUT 2004

  28. Network-on-a-Chip Basics – cont. 1 • Current techniques such as point-to-point connections is acceptable when only a small number of blocks. • For SoC, a richer set of interconnect schema should be explored. • Solving the latency vs. throughput trade-off now requires to take in consideration a large number design parameters, like pipeline stage, arbitration, synchronization, routing and repeating schemes. • Communication design has to begin at higher levels of abstraction than the architecture and RTL level. ©TUT 2004

  29. Network-on-a-Chip Basics – cont. 2 • We believe that a layered approach similiar to that defined by communication networks community (ISO-OSI). • Separating the communication protocol functions into layers that interact via well-defined interfaces allows for a decomposition of design problems. • The layered-stack approach to the design of the on-chip inter-core communications has been called the network-on-chip (NOC) methodology. ©TUT 2004

  30. Network-on-a-Chip Basics – cont. 3 • Since 2000, NOC design has attracted major attention and multiple approaches have been proposed. • The Virtual Socket Interface (VSI) Alliance has developed a standard interface to connect virtual component (VCs) to on-chip bues. • The Sonics approach de-couples the design of the communication among IPs. • One important aspect of the NOC problem – the reservation of of network resources such as buffer and bandwidth – is addressed by B. Dally, who proposes the flit-reservation flow control. ©TUT 2004

  31. Network-on-a-Chip Basics – cont. 4 • A new generation of methodologies and tools needed to be developped and they should be centered along the following key tenets: • By applying a decipline to on-chip communication design transition from ad-hoc SoCs to deciplined IC platforms. • Should be based on formal Models of Computation and support a correct-by-construction snythesis design flow and a set of analysis tools for broad design exploration. • Maximaize re-use with the definition of a set of interfaces between layers. • Provide an application programmer with a set of APIs abstracting architecture details. ©TUT 2004

  32. The OSI Reference Model Applied to NOCs • The OSI Reference Models is a framework that allows us to classify and describe network protocols. • The seven OSI layers for on-chip applications • Physical Layer: The NOC physical layer protocols define such things as signal voltages, timing, bus width, and pulse shape. A paticular concern at this layer is the synchronization of signals. • Data link Layer: is responsible for reliable transfer of data over the physical link, and may incude error detection and correction functions. • Network Layer: provides a topology-independent view of the end-to-end communiation to the upper level protocol layers. ©TUT 2004

  33. The OSI Reference Model Applied to NOCs – cont. 1 • Transport Layer protocols establish and maintain end-to-end connections. This abstraction hides the topology of the network, and the implementation of the links the make up the network. • Session Layer protocols add state to the end-to-end connections provided by the transport layer. A common session protocol is synchronous messaging, which requires that the sending and receiving compoments rendezvous as the message is passed. • Presentation Layer is concerned with the represnetation of data whithin messages. Protocols at this level convert data into compitable formats. • Application Layer would define a function that does exactly this by utilizing the functions defined at lower satck layers. ©TUT 2004

  34. The OSI Reference Model Applied to NOCs – cont. 2 • OSI stack model is scalable. • In most cases, it is not necessary to implement protocols at all of the OSI stack layers to provide this high-level functionality. ©TUT 2004

  35. A NOC Excample: The Pleiades Platform • Pleiades represnets a reconfigurable integrated circuit for DSP applications • Demonstrates how the NOC layers of abstraction are applicable to existing designs. • A heterogeneous collection of satellites such as ALUs, memories, processors, FPGAs, and multiply accumulators. • From communication perspertive, the computation at each satellite is arbitrary because each is wrapped in a inter-setellite communication interface. ©TUT 2004

  36. A NOC Excample: The Pleiades Platform – cont. 1 • The Pleiades Platform for Communication Application ©TUT 2004

  37. A NOC Excample: The Pleiades Platform – cont. 2 • The interface is actually the physical layer in the NOC framework, because it specifies the signal difinations, timing, and synchronization between two setallites. • Additionally, each satellite operates on a local clock, which is not necessarily coincident with the other satellite clocks. • Thus, the interface is self-timed through a two-phase asynchronous handshaking scheme. • Lastly, the communication reduces power consumption through reduced-swing signaling. ©TUT 2004

  38. A NOC Excample: The Pleiades Platform – cont. 3 • The physical layer of the Pleiades Plaform protocol stack: • globally asynchronous, locally synchronous(a); • and reduced swing signal (b). ©TUT 2004

  39. A NOC Excample: The Pleiades Platform – cont. 4 • In network layer, the interconnect consists of a two-tired hierarchical mesh to provide energy efficiency as well as the required flxibility. • Local level, universal switchboxes provide a method for programatically connecting wires with a cluster. • Global level provides switchboxes connected in a large-granularity mesh for inter-cluster communication. ©TUT 2004

  40. A NOC Excample: The Pleiades Platform – cont. 5 • The pleiades platform clearly demostrate how a formal structure NOC-based approach can help to make the mapping of complex algorithms on concurrent architectures manageable, verifiable, predictable, and automatable. • The opportunities offered by NOCs are however much broader and more far-reaching. ©TUT 2004

  41. Summary and Perspective • The combination of design complexity, deep-submicron challenges and economics is increasing undermining traditional design approach such as ASIC. • Platform-based methodology presents an alternative approach which address a number of concerns through • High level abstraction; • High level re-use; • A large role of ”Soft design”. ©TUT 2004

  42. Summary and Perspective – cont. 1 • The core of platform is the communication strategy, that is the way how functions interact with each other. • The rising importance of a formal NOC approach in light of the increasing use of concurrency. • NOC can also help to address some crucial DSM problems such as power, reliability and synchronization. • So far however, we just have baby steps. ©TUT 2004

  43. Something Beyond – Wire Repalcing ? • Optics Joined with Silicon? • Optical Interconnects to Silicon Chips? ©TUT 2004

  44. Something Beyond – Wire Repalcing ? http://fuji.stanford.edu/events/Spring03/ ©TUT 2004

  45. Thank You ! ©TUT 2004

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