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Controller Craps Dice Game. Switching and Logic Lab Standard Laboratory Exercises. Craps. Review rules (view from state information) ASM chart game State diagram FSM for controller Integrate dataflow and control Game Done!. Rules of Craps Dice Game.
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Controller Craps Dice Game Switching and Logic Lab Standard Laboratory Exercises
Craps • Review rules (view from state information) • ASM chart game • State diagram • FSM for controller • Integrate dataflow and control • Game Done!
Rules of Craps Dice Game • After rolling the dice (two six-sided die), the sum is tested. • If the sum is • 7 or 11, the player wins; • if it is 2, 3, or 12, the player loses. • Otherwise, the sum is either 4, 5, 6, 8, 9, or 10 and is saved as the point and the player must roll again. . • If the new sum • equals the point, the player wins; • if it is 7, the player loses. • Otherwise, the player must roll again. • Play continues until the player wins or loses
ASM Chart Symbols • Actions relate to • States (reset, roll dice, roll done) and • Outputs to dataflow (Sp and Roll) and outside world (Win and Lose) • Decisions relate to inputs from dataflow (D7, D711, D2312, EQ) and outside world (Rb and Reset)
Roll Dice Y N Rb Y N D711? Win Lose Y Y N N Reset Reset ASM Chart Add your actions and decisions here.
State Diagram State Description sReset Reset sFirstRoll First Roll sStorePoint Store Point sPlayerWins Player wins sPlayerLoses Player loses sWaitNextRoll Wait for next roll sNextRoll Next Roll sEndNextRoll End next roll 8 states
State Diagram • Partial Moore Model • Complete transitions • Note states not in sequence • sResetsFirstRoll sStorePoint ••• sReset
Craps Controller Entity ENTITY Controller IS PORT ( Rb,Reset,Clk : IN BIT; --external D7,D711,D2312,Eq : IN BIT; --internal Roll,Sp : OUT BIT; --internal Win,Lose : OUT BIT; --external END Controller;
Behavioral Architecture ARCHITECTURE Behavioral OF Controller IS TYPE STATE_TYPE IS (sReset, sFirstRoll, .....); SIGNAL state : STATE_TYPE; BEGIN --Place behavioral description here END Behavioral;
State Logic --Finite State Machine FSM: PROCESS BEGIN --Insert CASE statement here END PROCESS FSM;
Case Statement CASE State IS WHEN sReset => --Reset State IF Rb = ‘0' THEN State <= sReset; ELSE State <= sFirstRoll; END IF; -- place the rest of the cases here END CASE;
Moore Output Logic --output combinational logic Sp <= '1' WHEN State = sStorePoint ELSE '0'; Roll <= Win <= Lose <= Example
Build Simulation State by State and Transition by Transition
Build Simulation • State by State (See previous slide) • Transition by transition (D7, D711, D2312, EQ, Reset and Rb • Get 100% coverage by going through all states and taking all possible transitions out of given state
Controller Test and Verification • Enter Controller as VHDL • See course web page for template • Requires some additional typing • Analysis and Synthesis • Assign Pins • Compile until error and warning free • Simulate controller inputs • Check controller outputs • Program • Exercise
DataflowCraps CrapsController OUTPUT DSL[0..6] Rb INPUT Roll DSL[0..6] Rb Roll VCC Clk INPUT OUTPUT DSR[0..6] Reset INPUT Clk DSR[0..6] Reset Sp VCC VCC OUTPUT Win OUTPUT Sum[3..0] SP Sum[3..0] Clk Win OUTPUT Lose D7 D7 Lose OUTPUT State[2..0] D711 D711 State[2..0] D2312 D2312 Eq Eq OUTPUT Point[3..0] Point[3..0] inst1 OUTPUT D7 OUTPUT D711 inst OUTPUT D2312 OUTPUT Eq Craps Project • Copy all BDFs and VHDLs to new folder • Create new project (with unused pins as Tristate inputs) • Create symbols of dataflow BDF and Controller VHDL • Interconnect
Craps • Analysis and Synthesis • Assign Pins • Skip Simulation • Program and Play • Did it work properly? • Obtain signature
Unused Pins as Tri-State Inputs • Select “Assignments” • Select “Device” • Select “Device & Pin Options” • Select “Unused Pins” Tab • Select “As inputs, tri-stated” • OK