FPIX - Electronics

1. FPIX - Electronics Steve Schnetzer Rutgers University US CMS DOE/NSF Review April 12, 2000

2. FPIX - Electronics • System Components • Token Bit Manager (TBM) Rutgers • controls readout • prototype by summer ‘00 • Front End Controller (FEC) Fermilab • control network master • prototype by summer ‘00 • High Density Interconnect (HDI) Rutgers • circuit for connecting front-end elements • prototype summer ‘01 • Optical Link Johns Hopkins • digital link test -- fall ‘00 • analog link test --summer ‘01

3. FPIX - Electronics

4. FPIX - Electronics • TBM Functions • Control readout through token pass • Maintain event synchronization • Pass triggers and clears to ROC’s • Stack triggers awaiting token pass • Disable event readout if more than eight triggers stacked • Write token pass header and trailer • Serve as hub for slow control commands

5. FPIX - Electronics • TBM Status • Functionality defined • LVDS driver and receiver designed • Submitted in DMILL (8/99, 11/99) • Schematic blocks designed and simulated • 16-deep, 8-bit FIFO stack • token control • slow control interface • sequential control logic • trigger encoder/decoder • counters and status registers • header/trailer output

6. FPIX - Electronics Sequencer Token Control • TBM Block Schematic Stack Trigger Counter Header/Trailer Shift Register Trailer Status Register Header Status Register Trigger Decoder Trigger Encoder

7. FPIX - Electronics • LVDS Driver • DMILL layout

8. FPIX - Electronics • LVDS Receiver • DMILL layout

9. FPIX - Electronics • TBM Schedule (Completion by end of ‘00) • Implementation of schematic design in FPGA • Construction of test stand and test DAQ • Stand alone tests of FPGA TBM. Check: • correct response to trigger inputs • stack contents • validity of header and trailer • proper setting of status bits • System tests with FED, FEC and Optical Links • FECOptical linkTBM Optical link FED • Decision: Honeywell vs. DMILL

10. FPIX - Electronics • TBM Schedule (Completion by end of ‘01) • System Test of TBM with ROC’s and HDI • uses LVDS drivers/receivers • Layout and submission of ASIC TBM • Stand alone test of ASIC TBM • System Test of ASIC TBM • TBM, ROC’s , HDI, FEC, FED and Optical Links • Ready for production (early ‘02)

11. FPIX - Electronics • TBM Issues • Finalization of functionality • Honeywell vs. DMILL decision • needed by end of year • Decision on DAC • ROC design ? • Alternative digital output ? • Size of chip • likely dominated by pin outs • needed for HDI and panel design

12. FPIX - Electronics • Control Network Functions • Programming of ROC’s • setting of trim bits • trigger latency • set calibration mode • reset • Programming of TBM • enable/disable passing of triggers/tokens • reset • Programming of PLL • phase shift of clock • Setting of Laser Driver Thresholds

13. FPIX - Electronics • Control Network Components • One independent network per blade • One FEC channel per network • serves as sole network master • Four front-end network hubs for each blade • hubs will be implemented as components of TBM • Each hub will have four I2C ports • controls four group of ROC’s or • Laser, PLL, DCU, spare

14. FPIX - Electronics • Control Network Issues • Refresh ROC threshold trims every 10 minutes •  180 k pixels per network • 72 bit transfer per refresh (write/read back) • use empty orbit  100 s every 0.1 second •  clock speed = 20 MHz • Use I2C-like standard • slow clock speed for talking to PLL, Lasers • Adaptable for both barrel and forward pixels • flexibility to allow changes in modularity • up to 16 hubs per network

15. FPIX - Electronics • Control Network Architecture • FEC  Hubs • Four optical fibers • 40 MHz clock with embedded L1 trigger (FEC  TBM’s) • Control clock (FEC  Hubs) • Control data (FEC Hubs) • Control data (FEC Hubs) • Hubs  Port Devices • Two bi-directional I2C lines • Clock (Hub  PortDevices) • Data (Hub  PortDevices)

16. FPIX - Electronics • Control Network Architecture

17. FPIX - Electronics • Control Network Schedule (by end ‘00) • Single channel FEC prototype • Hub designed and implemented in FPGA • System test • FEC, Hub and Optical Link

18. FPIX - Electronics • System test 2000 • FEC • FPGA TBM • Digital Optical Link • FPGA Hub • PLL • FED

19. FPIX - Electronics • HDI Definition • 4-layer flex circuit • Covers panels on blade • folded over at edge to cover both sides of blade • TBM’s and groups of ROC’s glued to surface • Provides high-density interconnections between: • groups of ROC’s • TBM’s • Lasers/Photodiodes • PLL • Pigtails: • power in on one side • signals out to laser drivers on other side

20. FPIX - Electronics • HDI Status • Have been awaiting ROC pinout decision before proceeding with final design • decision made in March • Proof of principle design of full blade HDI • List of potential vendors compiled • Phase 1 test of cross talk completed • high-speed lines running next to chip

21. FPIX - Electronics • HDI Layout • Full blade • 4-layer flex circuit • power in one side • signals out to Port Card other side

22. FPIX - Electronics • Cross talk • Honeywell PSI30 chip • sensor bump-bonded • single-ended line • directly above sensor • line parallel to columns • 1 nsec rise time • 40 e- rms / Volt • common to all columns • intrinsic chip noise • 80 electrons • in real case: • ±0.2 volt differential • directly under chip

23. FPIX - Electronics • HDI Schedule (Completion by end of ‘00) • Definition of ROC pinouts • done • Layout of prototype HDI • Decision on trace width and pitch needed • selection of technology • selection of vendor(s) • Production of prototype • covering one group of ROC’s • Test of cross talk from lines running under ROC’s

24. FPIX - Electronics • HDI Schedule (Completion by end of ‘01) • System Test of HDI • ROC’s and FPGA TBM • Test of radiation hardness • glue, material • Test of thermal properties • Definition of TBM pinouts • Layout and production of full blade HDI • System test • ROC’s and chip Quad-TBM • Full blade test (in ‘02)

25. FPIX - Electronics • HDI Issues • Definition of ROC pinouts • Definition of TBM pinouts • Cross talk • Number of layers • Trace width and pitch • Composition • Thermal properties • Radiation hardness of glues

26. FPIX - Electronics • ROC Gain Uniformity

27. FPIX - Electronics Vtrim = -1.1 V Vc • ROC Thresholds Vcal= -1.10V Vc-high 1 off Vcal= -1.06V 2 3 VTRB 4 Vtrim 5 3 bits 6 Vc 7 Vcal= -1.02V Vc-low Vthr = Vc + Vtrim xVTRB Vc