Reconfigurable Computing (EN2911X, Fall07) Lecture 15: SystemC (3/3)

1. Reconfigurable Computing (EN2911X, Fall07) Lecture 15: SystemC (3/3) Prof. Sherief Reda Division of Engineering, Brown University http://ic.engin.brown.edu

2. Integer data types • Supported native C++ synthesizable data types • long long (64 bits) • long (32 bits) • int (32 bits) • short (16 bits) • char (8 bits) • bool (1 bit) • SystemC also allows further refined storage types • sc_bit • sc_bv <width> • sc_int <width> • sc_uint <width> • sc_bigint <width> • sc_biguint <width>

3. Full supported for compilation with VisualC++ and systemC library Supported for synthesis by Celoxica’s Agility compiler only if they can be evaluated during compilation time → Any calculation involving float point must evaluate to a constant Floating-point data types Synthesizable example sc_int<16> SinTable [128]; for(int i=0; i < 128; i++ ) { double index=(double) i; double angle=2.0*PI*(index/128.0); double sineangle=sin(angle); SineTable[i]=sc_uint<16>(sineangle*32767.0); } Not synthesizable example sc_in<float> in; float x; X=in.read();

4. Full supported for compilation with VisualC++ and systemC library For synthesis with Agility compiler, an array is synthesizable if its elements are of a synthesizable type and its size is compile-time determinable Arrays Although the array is not synthesizable, the members are only used during compilation time and are cat to type int Synthesizable example int temp, array[100]; sc_in <int> in; For(int y=0; y < 100; y++) { in.read(temp); array[y]=temp; wait(); } #include <math.h> float l[10]; for(int y=0; y<10; y++) l[y]=log10((y+1)*10); //… sc_out <int> out; for(int y=0; y < 10; y++) out.write((int)l[y]);

5. Full supported for compilation with VisualC++ and systemC library Agility supports pointers subject to the restriction that Agility can always determine the target of the pointer A pointer is synthesizable if it is a pointer to a synthesizable type, and the value to which the pointer points is compile-time determinable Pointers Resolvable pointer void clear(char *a, char *b) { *a=255; *b=255; } sc_out <unsigned char> out; unsigned char x, y; clear(&x, &y); out.write(x); }

6. Full supported for compilation with VisualC++ and systemC library Operator new is supported at compiler time but not at runtime. delete operator is not supported Each action in a switch must have a break statement. Fall through is not allowed If a function to be synthesized, its body must only contain code that within Agility synthesizable subset General recursion is not supported for synthesis Other considerations for synthesis

7. Example using synthesis and compilation flow Rest of code (testbenches, SW code) Synthesizable subset Celoxica agility synthesizer Verilog/edif Visual C++ SystemC library Quartus II executable

8. Celoxica’s Agility compiler tutorial

9. Starting adding files to your project

10. Adjust the project settings to use the Cyclone II devices

11. Add your file and write your class declaration

12. Add the main synthesis entry point Not the most direct implementation

13. Build your project

14. Check the CDFG and Verilog output

15. Sometimes the Celoxica compiler changes the name of input/output outputs when it exports to Verilog so make sure to fix this in Quartus II assignment editor Copy the Verilog file into Quartus II Then build and download to the FPGA

16. KEY[0] tester orgate clk KEY[1] LEDG What if we want to verify and simulate before downloading to the FPGA? Choose Visual C++ Add a tester.h for tester module

17. Add the main body

18. Hit Build and then run the executable Build indirectly invokes the command line compiler of VC (cl) which links your compiled code with SystemC.lib

19. If you like to synthesis again, make sure to mark the files you want to synthesize Choose Verilog as your desired output again Exclude tester.h and orgate_exe.cpp

20. Objective: Learn SystemC using both the synthesis and compilation flows. This time it is a simple example. We will design an 8-bit ALU. Use the 18 switches in the DE2 board to achieve your target: 8 switches give the binary of the first unsigned integer 8 switches give the binary of the second unsigned integer 2 switches give the ALU operation (addition, subtraction, multiplication and XORING) In your report, make sure to include the SystemC code, the executable output print of simulations, and the FPGA resource utilization. You have to send me by email your projects archived for both the SystemC design and the Quartus II files Lab due before Thanksgiving holiday (Thur 22nd) Tutorials and Celoxica manual uploaded at the class webpage and also available to download from Engineering website HW/Lab 3