Layout Design Rules for Optimum Circuit Yield and Reliability

1. Chapter 3 Layout design rules

2. Introduction • Layout rules is also referred as design rules. • It is considered as a prescription for preparing photomasks. • Provides a link between circuit designer and processor engineer during manufacturing phase. • Design rules specify geometric constraints on the layout artwork. • Objective: • To obtain a circuit with optimum yield. • To minimize the area of the circuit. • To provide long term reliability of the circuit. • Design rules represent the best compromise between performance and yield: • More conservative rules increase yield. • More aggressive rules increase performance. • Design rules represent a tolerance that ensures high probability of correct fabrication - rather than a hard boundary between correct and incorrect fabrication.

3. Layout or Design Rules • Two approaches to describing design rules: • Lambda-based rules: Allow first order scaling by linearizing the resolution of the complete wafer implementation. • To move a design from 4 micron to 2 micron, simply reduce the value of lambda. • Worked well for 4 micron processes down to 1.2 micron processes. • However, in general, processes rarely shrink uniformly. • Probably not sufficient for submicron processes. • Micron rules: List of minimum feature sizes and spacings for all masks, e.g., 3.25 microns for contact-poly-contact (transistor pitch) and 2.75 micron metal 1 contact-to-contact pitch. • Stated at some micron resolution, alpha() and beta ( ) rules. Basic feature size is defined in terms of  while minimum grid size is described by .  and  may related by a constant factor. • Normal style for industry.

4. Layout or Design Rules

5. Lambda-based p-well rules • A version of p-well rules loosely based on the JPL rules. • These rules are only representative and are the result of averaging a large number of processes. • The rules are defined in terms of: • Feature sizes • Separations and overlaps.

6. Mask No. 1:Thinox

7. Mask No. 2: P-well

8. Mask No. 3: Poly

9. Mask No 4: P-plus

10. Mask No 5: Contact

11. Mask No 5: Contact

12. Contact No 6: Metal

13. CMOS Design Rules • A layout resembles the top view of the IC • The layout design is 2-dimentional from the viewpoint of an IC designer. • in fact, designers normally do not control the depth dimension of an IC. The depth of a transistor source or the thickness of a metal wire is determined by the fabrication process. • The layout designer only decides the dimensions and locations of the transistors and interconnects them into the target circuit. • The minimum feature size of a technology is typically denoted by the narrowest width of a polysilicon wire that it can produce. • For instance, if the narrowest polysilicon wire in a technology is 1m wide, it is called 1 m technology. • Design rules capture the physical limitations of a fabrication process. • Design rules release designers from the details of fabrication so they can concentrate on the design instead.

14. CMOS Design Rules • In -based design rules (developed by Mead and Conway) the minimum feature size is 2. • For a 2m technology, =1mm • Different fabrication technologies apparently require different rules. • Drawbacks of scalable design rules: the layout produced according to scalable design rules are often larger than necessary. • For example, a minimum spacing of 4m may be ordered although in reality 3.2m is sufficient.

15. MOSIS Design rules • Scalable -based design rules are used in MOSIS projects. • http//:www.mosis.org • A subset of MOSIS scalable CMOS (SCMOS) design rules is used to provide an overview of their use.

16. The largest spacing is in the -based design rules is the minimum distance between diffusion regions of different types. (to avoid latch-up problem. • Minimum width of diffusion region is 3λ • Two unrelated diffusion regions of the same type have to be separated by at least 3λ

17. Polysilicon is used both as transistor gates and as short distance interconnection. • Minimum width of polysilicon wire is 2λ • And two unrelated polysilicon wires must be separated by as least 2λ

18. Legend

19. Legend

20. Legend

21. Legend

22. Example 1: symbolic layout for and inverter Layout Examples According to -based design rules, the smallest transistor channel is 2long and 3 wide (the minimum width of diffusion region). However, in the following figure the width of transistor has been increased to 4 so that a diffusion contact (4 X 4 required) can be readily made. This 2 X 4 transistor is referred as the minimum size transistor. An inverter formed of minimum size transistors is called a minimum size inverter. Area: 42 X 15= 6302 Stick diagram

23. Layout Examples Example 3.1 :Alternative layouts for inverter Area of both: 40 X 18= 7202

24. Layout Examples Use 2 X 4 transistors to create a symbolic layout for a two NAND gate,

25. Example: Minimize the area of the NAND gate discussed in previous Example Ans: area reduction by 12% layout Examples

26. Example Design a layout for layout Examples • The design objective in this example is to form two rows of tranaiators. • All pMOS transistors should be in one row and all nMOS transistors should be in another row. • This layout structure eliminates the need to cross input signals.

27. Example: design the symbolic layout for the function with 2  X 8  transistors. layout Examples

28. Figure 3.28 (p. 97)Three series-connected nFETs.

29. layout Examples Figure 3.29 (p. 98)A parallel-connected FET patterning.

30. Figure 3.30 (p. 98)Alternate layout strategy for parallel FETs. layout Examples

31. Figure 3.31 (p. 99)Translating a NOT gate circuit to silicon.

32. Layout Examples Figure 3.32 (p. 100)Alternate layout for a NOT gate.

33. Figure 3.34 (p. 101)Non-inverting buffer. Layout Examples

34. Layout Examples Figure 3.35 (p. 101)Layout of a transmission gate with a driver.

35. Layout Examples Figure 3.37 (p. 102)NOR2 gate design.

36. Figure 3.39 (p. 103)Layout for 3-input gates. Layout Examples

37. Figure 3.40 (p. 104)Extension of layout technique to a complex logic gate. Layout Examples

38. Figure 3.41 (p. 105)Creation of the dual network. Layout Examples

39. Figure 3.42 (p. 105)A general 4-input AOI gate. Layout Examples

40. poly ndiff pdiff m1 m2 contact pFET nFET Stick Diagrams In the early days of MOS integrated circuits it was noticed that when a chip was illuminated with a white light source, each conducting layer had a distinct coloring associated with t when viewed under a microscope. This observation provided the basis for developing the technique:

41. An example : An Inverter

42. An example : NOR gate

43. Example