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OC-192 communications system block diagram

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OC-192 communications system block diagram

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    1. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 1 OC-192 communications system block diagram

    2. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 2 Transceiver block diagram:

    3. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 3 Transmitter Block Diagram

    4. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 4 Low-Frequency Input signals

    5. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 5 Illustration of Input Timing Regimes

    6. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 6 First-In/First-Out (FIFO) Circuit (1)

    7. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 7 First-In/First-Out Circuit (2)

    8. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 8

    9. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 9 16:1 Multiplexer Tree Structure Will discuss data path in next few slides. Notice also the presence of clock dividers. These will be discussed following.Will discuss data path in next few slides. Notice also the presence of clock dividers. These will be discussed following.

    10. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 10 2:1 MUX cell details

    11. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 11

    12. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 12

    13. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 13

    14. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 14 Clock Dividers Clock divider is an integral, and sometimes the most difficult part of the system to design.Clock divider is an integral, and sometimes the most difficult part of the system to design.

    15. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 15

    16. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 16 Sensitivity Curve Analysis

    17. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 17 Region II: Quasiperiodic behavior

    18. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 18 In reality, all high-speed clock signals are nearly sinusoidal.In reality, all high-speed clock signals are nearly sinusoidal.

    19. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 19 Effect of Transistor Sizes on Sensitivity Curve

    20. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 20 Alternatives to DFF-Based Clock Dividers

    21. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 21

    22. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 22 Ring-Oscillator-Based Divider

    23. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 23 Comparison of Sensitivity Curves

    24. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 24 Effect of Non-Ideal Clock Signals

    25. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 25 Result of nonideal half-rate clock is Periodic Jitter.

    26. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 26 Retimer eliminates this problem:

    27. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 27 Internal MUX Timing

    28. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 28 Serial Output 50? Line Driver Final stage is determined by 25Ohm ac resistance and desired output swing -- in this case 500mV. Previous stages scaled down appropriately until nominal internal buffer is used. Can use shunt-peaking throughout the driver. (Pause here.)Final stage is determined by 25Ohm ac resistance and desired output swing -- in this case 500mV. Previous stages scaled down appropriately until nominal internal buffer is used. Can use shunt-peaking throughout the driver. (Pause here.)

    29. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 29 Receiver Block Diagram

    30. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 30 DMUX Architecture

    31. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 31 1:4 DMUX Tree Structure

    32. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 32 1:2 DMUX cell details:

    33. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 33 Internal DMUX Timing

    34. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 34 Crosstalk in Transceivers Frequency pulling is similar to phenomenon of injection locking in clock dividers.Frequency pulling is similar to phenomenon of injection locking in clock dividers.

    35. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 35 Crosstalk Measurement

    36. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 36 Techniques for Reducing Transceiver Crosstalk

    37. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 37 SONET Jitter Specifications

    38. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 38 Jitter Generation (1)

    39. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 39 Jitter Generation (2) Change frequency to 9.95328 GHz.Change frequency to 9.95328 GHz.

    40. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 40 Jitter Generation (3)

    41. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 41 Jitter Generation (4)

    42. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 42 Jitter Generation (5)

    43. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 43 Jitter Generation (6) Bit rate used here is higher than 10G due to forward error correction.Bit rate used here is higher than 10G due to forward error correction.

    44. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 44 Jitter Tolerance (1)

    45. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 45 Jitter Tolerance (2) DerivationDerivation

    46. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 46 Jitter Tolerance (3)

    47. EECS 270C / Spring 2009 Prof. M. Green / U.C. Irvine 47 Jitter Transfer (Pause here.)(Pause here.)

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