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Fermilab Experiment attack deep questions in physics today…

Explore the frontiers of particle physics at Fermilab - Energy, Intensity, and Cosmic. Learn about experiments, timelines, and strategies to answer fundamental questions. Discover the computing and networking challenges driving the future of physics research.

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Fermilab Experiment attack deep questions in physics today…

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  1. Fermilab Experiment attack deep questions in physics today… R. Tschirhart, November 2010

  2. How do we find the answers? Three frontiers of particle physics R. Tschirhart, November 2010

  3. Fermilab Energy Frontier: Strategy & Timeline LHC ILC, CLIC or Muon Collider Tevatron LHC LHC Upgrades ILC?? LHC 2022 2019 2016 Now 2013 R. Tschirhart, November 2010

  4. Fermilab Intensity Frontier: Strategy & Timeline NOvA MicroBooNE g-2? SeaQuest MINOS MiniBooNE MINERvA SeaQuest Project X+LBNE m, K, nuclear, … n Factory ?? LBNE Mu2e Intensity 2022 2019 2016 2013 Now 4 R. Tschirhart, November 2010

  5. Fermilab Cosmic Frontier: Strategy & Timeline DM: ~1 ton DE: LSST WFIRST?? BigBOSS?? DE: LSST WFIRST?? DM: ~100 kg DE: DES P. Auger Holometer? DM: ~10 kg DE: SDSS P. Auger 2022 2019 2016 2013 Now R. Tschirhart, November 2010

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  8. Sample with bullet points First Bullet Second Bullet More Yet more Still more Less important Trivial LongBaselineNeutrino Experiment New Neutrino Beam at Fermilab… …Directed towards NSF’s proposed DUSEL Precision Near Detector on the Fermilab site 100 kT fiducial volume Water Cherenkov Far Detector 17 kT fiducial volume Liquid Argon TPC Far Detector 8 J.Strait, Fermilab - DOE Science & Technology Review July 12-14, 2010 10 R. Tschirhart, November 2010

  9. Some Computing and Networking Challenges the Fermilab Program • LHC: Data acquisition, handling, production, dbase management, distribution, analysis, stewardship. • Mu2e: Network-based streaming DAQ architecture • DES/WFIRST/LSST: Approaching LHC, 10’s of PBytes, SOCs. • Next generation LQCD & HPC: GPUs, next generation networks. • “Stage-II” LHC trigger upgrades…. • Free space “wireless” data transmission within collider detectors. R. Tschirhart, November 2010

  10. LSST estimates courtesy Jeff Kantor & Erik Gottschalk R. Tschirhart, November 2010

  11. Extracting Data From the Center of the Onion R. Tschirhart, November 2010

  12. R. Tschirhart, November 2010

  13. Future DAQ architectures (Mu2e) In a typical streaming DAQ system (e.g., Nova), data fragments are collected by Readout Controllers, transmitted through an Event Building network (Gigabit Ethernet switch), and assembled/processed in the online processing farm. Detector 2-port Readout Controller Processor ... Event Building Network This works fine at a few GBytes/sec, but ... R. Tschirhart, November 2010

  14. Detector 3-port Readout Controller Processor ... Event Building Network This has other advantages - more efficient switch utilization (switch connections are bidirectional, so we use half as many ports) - complete events are assembled in ROC memory before being sent to the processor … the same FPGA that does the readout and event building can do a significant amount of pre-processing (including a full L1 Trigger, if desired). See for example: http://www.altera.com/literature/wp/wp-01142-teraflops.pdf R. Tschirhart, November 2010

  15. Event Building Network 24 port, 10 Gbps switch 60 Ports (60 Gbytes/sec) Scalable (156 ports) R. Tschirhart, November 2010

  16. Detector 3-port Readout Controller Processor Two 60 port networks 120 GBytes/sec peak bandwidth … 3-port Readout Controller Processor R. Tschirhart, November 2010

  17. Mu2e Processing Considerations Current processor technology - 4 or 6 high performance cores per processor, 2-4 processors per server - this will increase to 8 or 16 cores per processor “Many Core” processors are now in development for large scale data centers - Tilera, Intel, ARM, … - available next year - lower performance per core, but many more cores Pictured: Tilera 100 core processor...800 cores per 2U server...16,000 cores per rack http://www.tilera.com/products/processors/TILE-Gx_Family See also: Intel “Knight’s Corner” program http://www.intel.com/pressroom/archive/releases/2010/20100531comp.htm?cid=cim:ggl|mic_us_gen|ks1569D|s

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