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ECE3055 Computer Architecture and Operating Systems Lecture 1 Introduction

ECE3055 Computer Architecture and Operating Systems Lecture 1 Introduction. Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Institute of Technology. Objectives  To Learn. Core concepts of microprocessor architecture ISA (review of 2030) Pipelining

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ECE3055 Computer Architecture and Operating Systems Lecture 1 Introduction

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  1. ECE3055 Computer Architecture and Operating SystemsLecture 1 Introduction Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Institute of Technology

  2. Objectives  To Learn • Core concepts of microprocessor architecture • ISA (review of 2030) • Pipelining • Hazards • Cache/Memory hierarchy • Memory management • Core concepts of operating systems • Processes/threads • Protection • Resource Management • Scheduling • File System

  3. Course Information • Web page: http://www.ece.gatech.edu/~leehs/ECE3055 • Will be constantly updated, so check it out regularly • Prerequisite: ECE2031 Digital Design Lab • Textbooks • Patterson and Hennessey, Computer Organization & Design: The Hardware/Software Interface (3rd edition), Morgan Kaufmann, 2004. ISBN 1-55860-604-1. • Silberschatz, Galvin, and Gagne, Operating System Concepts with Java (6th edition), John Wiley, 2004. ISBN 0471489050.

  4. Grading Policy • 5 Programming Assignments: 35% (5, 10, 10, 5, 5%) • Individual work, no collaboration • Due in the first 5 min before class starts • No late turn-in will ever be accepted • Exams • 3 in-class exams: 45% (15% each, dates TBD) • Final: 20% (date on Oscar) • Final Grade is relative to your peer in class

  5. Part I: Patterson & Hennessy book

  6. Introduction • Rapidly changing field: • vacuum tube -> transistor -> IC -> VLSI (see section 1.4) • doubling every 1.5 years:memory capacity processor speed (Due to advances in technology and organization) • Things you’ll be learning: • how computers work, a basic foundation • how to analyze their performance (or how not to!) • issues affecting modern processors (caches, pipelines) • Why learn this stuff? • you want to call yourself a “computer scientist” • you want to build software people use (need performance) • you need to make a purchasing decision or offer “expert” advice

  7. Moore’s Law Core 2 Duo (Conroe) 291 millions, July 2006 P4 Extreme Ed. 178 millions w/ 2MB L3 IBM latest POWER5 has 276 million transistors Intel Dual-Core Xeon (P4-based Tulsa) w/ 16MB unified L3: 1.328 billion, 2006 42 millions 2,250 Exponential growth Transistor count will be doubled every 18 months  Gordon Moore, Intel co-founder

  8. Integrated Circuits Capacity

  9. Feature Size We are currently at 0.09µm and moving towards 0.065µm

  10. Average Transistor Cost Per Year

  11. What is a computer? • Components: • Processor(s) • Co-processors (graphics, security) • Memory (disk drives, DRAM, SRAM, CD/DVD) • input (mouse, keyboard, mic) • output (display, printer) • network • Our primary focus: the processor (datapath and control) • implemented using millions of transistors • Impossible to understand by looking at each transistor • We need...

  12. main() { int i,b,c,a[10]; for (i=0; i<10; i++)… a[2] = b + c*i; } High Level Language Compiler … lw r2, mem[r7] add r3, r4, r2 st r3, mem[r8] Assembler Abstraction • Delving into the depths reveals more information • An abstraction omits unneeded detail, helps us cope with complexity • What are some of the details that appear in these familiar abstractions? ISA

  13. A Typical PC System Architecture

  14. A Typical PC Motherboard (D975XBX)

  15. A Typical PC Motherboard (D975XBX)

  16. Instruction Set Architecture • A very important abstraction • interface between hardware and low-level software • standardizes instructions, machine language bit patterns, etc. • advantage: different implementations of the same architecture • disadvantage: sometimes prevents using new innovationsTrue or False: Binary compatibility is extraordinarily important? • Modern instruction set architectures: • 80x86 (aka iA32), PowerPC (e.g. G4, G5) • Xscale, ARM, MIPS • Intel/HP EPIC (iA64), AMD64, Intel’s EM64T, SPARC, HP PA-RISC, DEC/Compaq/HP Alpha

  17. Where we are headed • Performance issues • A specific instruction set architecture • Arithmetic and how to build an ALU • Constructing a processor to execute our instructions Pipelining to improve performance • Memory: caches and virtual memory • I/O • I will try to cover as much as possible, but do not forget we have another half of the semester for OS

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