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Ideas for FE electronics: Features for commissioning, debugging etc

Ideas for FE electronics: Features for commissioning, debugging etc. Time alignment == aligning the BXIDResets. BX0. BX1. BX2. BX3. BX4. BX5. BX6. BX7. BX8. BX9. BX10. BX11. BX12. BX13. BX14. BX15. BXIDRst -SODIN. BXIDRst A. BXID A. 3562. 3563. 0. 1. 2. 3. 4. 5. 6.

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Ideas for FE electronics: Features for commissioning, debugging etc

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  1. Ideas for FE electronics:Features for commissioning, debugging etc Upgrade Electronics, 13/06/2013

  2. Time alignment== aligning the BXIDResets Upgrade Electronics, 13/06/2013

  3. BX0 BX1 BX2 BX3 BX4 BX5 BX6 BX7 BX8 BX9 BX10 BX11 BX12 BX13 BX14 BX15 BXIDRst -SODIN BXIDRstA BXIDA 3562 3563 0 1 2 3 4 5 6 7 8 9 10 11 12 13 BXIDRstB BXIDB 3560 3561 3562 3563 0 1 2 3 4 5 6 7 8 9 10 11 ‘Beam’ data in A and B Beams collide in only one BX (or a few well-spaced BXs) Detector A sends a packet with data and BXID = 4 Detector A sends a packet with data and BXID = 2 Difference used to align BXIDResets H3653 H0 H1 H3653 H0 H1 H2 H3 H4 H2 Data2 Data4 H5 H3 H4 H5 H6 H7 H6 H7 Note that this requires EITHER sufficient number of BXID bits to unambiguously identify the correct BX OR data packets from every BX (or both!) Upgrade Electronics, 13/06/2013

  4. Diagnostics During commissioning, need some handles for debugging. We should have useful features like: Substitute the data with fixed patterns or other info Special running modes set by ECS (+TFC-alignment-mode) Pattern size can match the link bandwidth (no buffer overflow) 2. Transmit the full 12-bit BXID + length without data payload => very useful for time alignment 3. Nominal running will have the occasional truncated event => buffer full or Big-Event What if we have many of these (eg due to a bad threshold)? How will we tell what is wrong? Can we add info to the truncated events to indicate the reason for the truncation? Upgrade Electronics, 13/06/2013

  5. Using the GBTX Upgrade Electronics, 13/06/2013

  6. Control Signals to/from GBTX GBTX asserts ‘ready’ signals when it is ready to transmit/receive time for locking of PLLs, DLLs, data alignment etc After power-up, the FE should wait for these to assert txRdy = readiness of transmitter rxRdy = readiness of receiver GBTX has two ‘frame-types’, differentiated by two different 4-bit headers For transmitter: the FE selects the ‘frame-type’ using the txValid control For receiver: the GBTX asserts/deassertsrxValid according to the frame it receives Same functionality mirrored in the GBT-FPGA (Tell40) => we can use this feature for flagging frames (eg invalid data) tx/rxValid = 0: H = 1010 tx/rxValid = 1: H = 1001 Upgrade Electronics, 13/06/2013

  7. Data valid signals in transmission data frames 80 80 FE buffer GBTX FPGARX If there is more than one FE buffer driving a GBTX, then the FE must make its own dataValid bit in its data field. This is included in the GBTX frame. txValid rxValid 39 39 GBTX FPGARX FE buffer dataValid dataValid 39 39 FE buffer dataValid dataValid txValid Upgrade Electronics, 13/06/2013

  8. Data protection If you want to use Widebus Mode, remember that the data is NOT protected against SEUs (or more conventional bit errors on the link) You should estimate the rate and impact such errors have on your system Upgrade Electronics, 13/06/2013

  9. Data interface between FE and GBTX GBTX uses ePorts: 80, 160 or 320 Mbit/s One GBTX-frame per 40MHz: 80 bits (FEC mode) or 112 bits(wideBus) 80 each ePort handles 2 bits of frame per 40MHz 160 4 320 8 5 links @ 320Mb 5 links @ 320Mb 10 links @ 320Mb GBTX GBTX ePorts ePorts FE FE eg FEC, 320 4.8 Gb 4.8 Gb FE GBTX Same for received data ie TFC/ECS links 10 @ 320Mb 4.8 Gb FE 10 @ 320Mb 4.8 Gb Upgrade Electronics, 13/06/2013

  10. Eport signals GBTX data in (80,160,320) data in (80,160,320) data in (80,160,320) eportRX eportRX eportRX data out (80,160,320) data out (80,160,320) data out (80,160,320) eportTX eportTX eportTX clock out (40, 80,160,320) clock out (40, 80,160,320) clock out (40, 80,160,320) Upgrade Electronics, 13/06/2013

  11. Data from FE to GBTX Data sampling in GBTX ePortRX: 320 Mbit/s example Data[7:0] Data from FE chip Data[15:8] GBTX frame deserialiser Data[79:72] Fine phase adjustment Adjustable delay 40MHz 320 Mbit/s bit-stream X 10 Shift register X 10 GBTX 320MHz Delay line shifts phase of data to align it with local 320MHz clock. Fine adjustment. Automatic tracking or manual setting. Deserialiser converts serial stream at 320Mbit/s into parallel 8-bit word synchronous with local 40MHz clock In 320Mbit/s FEC mode, 10 ePorts are used. Each receives 8 bits of the 80-bit GBTX frame. In 320Mbit/s widebus mode, 4 extra ePorts are used to add 32 bits to the GBTX frame. Data arrives at unknown phase wrt to GBTX internal clock Upgrade Electronics, 13/06/2013

  12. Fine phase adjustment made in GBTX 320 MHz clock X X X X X Y Y Y Y Y Z Z Z Z Z delay0 delay1 delay2 delay3 delay4 Upgrade Electronics, 13/06/2013

  13. GBTX ePortRX will handle FINE time alignment of bit stream BUT have to ensure that the 8 bits in the 320Mbit/s stream arrive at the correct time wrt 40 MHz clock in GBTX deserialiser Data[7:0] Data[15:8] A deserialiser B C 40MHz 320 Mbit/s bit-stream Shift register 320MHz Shift register On edge of 40MHz clock, we want this Not this Not this Upgrade Electronics, 13/06/2013

  14. Requirements for FE Fine phase alignment: requires transitions in the data => FE must guarantee edges in the data stream Coarse alignment to get 80, 160 or 320 Mbit/s stream lined up with 40MHz in GBTX ie data packet is in one GBT frame Suggestion: Implement adjustable delay in FE serialiser select Output of FE ePortTX going to GBTX 8 bits data @ 40MHz or test pattern Parallel load Shift clock 320 MHz Can use a test pattern like 11111110 to check the alignment Upgrade Electronics, 13/06/2013

  15. Data from GBTX to FE (TFC/ECS) NB ePort clock output goes with data stream So this clock can be used to sample the data in the FE But must ensure correct alignment with 40MHz clock in FE 80MHz clock from GBTX Example with 80Mb Simple deserialiser 80Mb serial stream from GBTX 40MHz Phase selectable deserialiser 80MHz clock from GBTX 80Mb serial stream from GBTX select 40MHz Alternative: repeat each TFC bit twice => effectively 40Mb (but introduces other limits) Upgrade Electronics, 13/06/2013

  16. Back-up slides Upgrade Electronics, 13/06/2013

  17. Alternative for time alignment: Use the BXID_counter offset 20 Orbit from LHC BXID reset in S-ODIN BXID reset In Det A BXID reset In Det B 5 10 TFC BXID 3543 3563 0 DetA BXID 3548 3563 0 DetB BXID 3553 3563 0 C=20 B=10 A=5 Upgrade Electronics, 13/06/2013

  18. 0 1 2 3 4 FE Buffer implementation 0 1 2 3 4 W W W W W W R R R R R R 0 1 2 3 4 Frame 0 goes to GBT: txDataValid=1 0 1 2 3 4 Frame 1 goes to GBT: txDataValid=1 0 1 2 3 4 No frame to GBT: txDataValid=0 0 1 2 3 4 Frame 2 goes to GBT: txDataValid=1 Upgrade Electronics, 13/06/2013

  19. Synch Synch HeaderOnly data filter Buffer control (packing) compression logic BX Veto NZS NZS Data Length HeaderOnly or BXVeto Buffer full Data Length Synchroniser Raw data data Big Event Buffer Data packet dataValid Compressed/Uncompressed data Data_available 40 MHz clock BXID Synch NZS Upgrade Electronics, 13/06/2013

  20. NZS Synch BXVeto HOnly Input to compression logic 0 0 0 0 BXID 12b Raw data BuffFull NZS Synch BXVeto HOnly Input to data filter 0 0 0 0 0 BXID 12b length Compressed data T packet from TFC filter 0 BXID n bits length Compressed data NZS Synch BXVeto HOnly Input to compression logic 0 0 1 1 BXID 12b Raw data BuffFull NZS Synch BXVeto HOnly Input to data filter 1 0 0 1 1 BXID 12b length Compressed data T packet from TFC filter 1 BXID n bits NZS Synch BXVeto HOnly Input to compression logic 0 1 0 0 BXID 12b Raw data BuffFull NZS Synch BXVeto HOnly Input to data filter 0 0 1 0 0 BXID 12b length Compressed data T packet from TFC filter 0 BXID 12 bits Synch pattern Length = buffer width = link frame width NB Synch bit can be set for a few cycles so that synch pattern is repeated a few times Upgrade Electronics, 13/06/2013

  21. NZS Synch BXVeto HOnly Input to compression logic 1 0 0 0 BXID 12b Raw data BuffFull NZS Synch BXVeto HOnly Input to data filter 0 1 0 0 0 BXID 12b Raw data T packet from TFC filter 0 BXID n bits Length = all 1s Raw data Upgrade Electronics, 13/06/2013

  22. Compromise for transmitting fewer BXID bits Frame Synch=1 T BXID n 12 bits Synch pattern Synch=1 T BXID n+1 12 bits Synch pattern Synch=1 T BXID n+2 12 bits Synch pattern Synch=0 T length T length BX n+3 BX n+4 data T length data BX n+5 data T BX with data 0 BXID n bits Length not 0 or F Compressed data BX with no data 0 BXID n bits Length=0 NZS 0 BXID n bits Length=F Uncompressed data HeaderOnly/BXVeto/BufferFull 1 0 BXID n bits Could be the same, without length field: But then can’t differentiate between the two cases 1 BXID n bits Big event 1 BXID n bits 1 Upgrade Electronics, 13/06/2013

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