Shaorui Li, Jie Ma, Gianluigi De Geronimo, Hucheng Chen, and Veljko Radeka

1. LAr TPC Electronics CMOS Lifetime at 300K and 77K Shaorui Li, Jie Ma, Gianluigi De Geronimo, Hucheng Chen, and Veljko Radeka Brookhaven National Laboratory, NY, USA • Outline: • Overview of basics on hot-carrier effects and lifetime. • CMOS Lifetime due to aging in TSMC 180nm: • A. CMOS lifetime in dcoperation: analog front-end ASIC; • B. CMOS lifetime ac operation: logic circuits and FPGAs. • 3. Thermal Cycling • 4. Future R&D Needs: Commercial FPGA and regulators

2. Introduction • Motivation: Low noise multiplexed readout of noble liquid detectors for neutrinos, nucleon decay, dark matter, double beta decay, in particular for very large liquid argon Time Projection Chambers (TPCs). • The goal: A continuous and unattended cryogenic operation for a long time (>10-20 years). • Electronics for noble liquid TPCs: It is known that CMOS operation at cryogenic temperature (~-200C) offers considerable advantages as compared to room temperature operation, with respect to speed, transconductance/drain current ratio (subthreshold slope) and noise. • The key question: How is the lifetime of CMOS affected by cryogenic operation? 2

3. Static Characteristics: Lower Power at 77K • Favorable for cryogenic operation: • higher gm -> lower noise • higher gm/ID -> lower power Design region (approx.) for low power and low noise at 77K (moderate inversion): gm increase by a factor of ~2. Asymptotic value at weak inversion:

4. CMOS Lifetime at Cryogenic Temperatures Introduction • Most failure mechanisms (e.g. electromigration, stress migration, time-dependent dielectric breakdown, and thermal cycling) are strongly temperature dependent and become negligible at cryogenic temperature. • The only remaining mechanism that may affect the lifetime of CMOS devices at cryogenic temperature is the degradation (aging) due to channel hot carrier effects (HCE). • The degradation mainly concerns NMOS devices - PMOS usually exhibits a lifetime much longer than NMOS. • Lifetime due to HCE aging: A limit defined by a chosen level of monotonic degradation in e.g., drain current, transconductance. The device “fails” if a chosen parameter gets out of the specified circuit design range. This aging mechanism does not result in sudden device failure. • The lifetime due to HCE at both the cryogenic temperature, as well as at room temperature, is limited by a predictable and a very gradual degradation (aging) mechanism which can be controlled or avoided by device design and operating conditions. In this study we have been following the basics established in the literature, e.g., Hu et al. (1985), and the practices adopted more recently by Chen&Cressler et al. (2006), as well as by industry. 4

5. Some hot electrons exceed the energy required to create an electron-hole pair, , resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current, (1) A very small fraction of hot electrons exceeds the energy required to create an interface state (e.g., an acceptor-like trap), in the Si-SiO2 interface, , for electrons (~4.6eV for holes). This causes a change in the transistor characteristics (transconductance, threshold, intrinsic gain). The time required to change any important parameter (the changes in different parameters are correlated) by a specified amount (e.g., gm by -10%) is defined as the device lifetime. It can be calculated as, (2) Overview of Basics on Hot-Electron Effects and NMOS Lifetime ~ ~ ~ q= electron charge λ=electron mean free path Em= electric field Ids= drain-source current W= channel width C1, C2 - constants • It has been widely recognized that Isubis a monitor for all hot-electron effects and it is the best predictor of device lifetime, becauseboth observable hot electron effects (electrical and optical) are driven by a common driving force –the maximum channel electric field Em , which occurs at the drain end of the channel. • The substrate current is connected to the lifetime (defined by any arbitrary but consistent criterion) by • (3)

6. Basics of Hot Carrier Effects • Degradation is due to impact ionization: • → shift in Vth and gm • Substrate current is a monitor of impact ionization • increases steeply with drain voltage • has a broad maximumat VGS≈ VDS/2 • Commercial technologies are rated > 10 years lifetime (10% gm shift) at T = 300 K, L = Lmin, VDS = nominal VDD+5%, VGS ≈ VDS/2 • A lower temperature results in increased mean free path λ increasing the substrate current Isub and gm degradation. Degradation is independent of temperature if the product λ(VDS – VSAT) is kept constant. • Accelerated lifetime test(well-established by foundries):transistor is placed under a severe electric filed stress(large VDS), to reduce the lifetime due to hot-electron degradation to a practically observable range, by a drain source voltage considerably higher (~80%) than the nominal voltage (1.8V for Lmin=180nm).

7. Stress Test Flow Chart and Layout of test NMOS transistors 2µm Test transistors, NMOS L=180nm, W=10µm (5 fingers x 2µm), designed to have negligible IR drop and power dissipation <15mW in stress tests to prevent temperature change due to self-heating.

8. Measurement Type I: “Stress Plot” The measured points at both 300K and 77K are very close to the characteristic slope for the interface state generation, ASIC design: Vds<1.5V CMOS in dc Operation: Analog Front-End ASIC • The projected lifetime at 300K is ~ an order of magnitude longer than at 77K. Reducing Vds at 77K by ~ 6% makes the lifetime equal to that at 300K. Design at low Ids/W for even longer lifetime.

9. Measurement Type II: Substrate Current Density Isub /W vs 1/Vds ASIC design: Vds<1.5V • One order of magnitude in substrate current Isub corresponds to three orders of magnitude in lifetime. At 77 K, Vds = 1.8 V projects a lifetime of ~5500 years. • Isub/W and 1/Vdsdistribution for all transistors in the analog front-end ASIC for LAr TPC (TSMC 180nm, 1.8V node) shows that all transistors are well below nominal voltage of 1.8V and at low Isub; Reduced Vds< 1.5 V results in essentially making HCE negligible and a very long extrapolated life time.

10. Noise Degradation: Less Degradation in PMOS NMOS L=180nm, W=10µm (5x2µm) PMOS L=180nm, W=10µm (5x2µm) 300 K 300 K 77 K 77 K • PMOS: much less degradation than NMOS • PMOS is used in the preamp input and, by design, it is the main noise contributor in the front-end ASIC.

11. CMOS Lifetime in AC Operation: Logic Circuits and FPGAs Long established (e.g. Quader&Hu et al.(1994), White&Bernstein (2006)] and adapted by foundries: considering the ac stress as a series of short dc stresses, each for effective stress timeteff during the switching cycle, strung together. The lifetime of digital circuits (ac operation) is extended by the inverse duty factor1/(fck teff ) compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequencies (up to 200 MHz) which may be needed for the TPC readout. Design guidelines for digital circuits and FPGAs: Keep the inverse duty factor 1/(fck teff )high . Additionally, reducing Vds by 10% adds an order of magnitude margin to the lifetime. • Rough estimation ofteff[Quader&Hu et al. (1994)]: • -1/4 of the gate voltage rise time for NMOS • -1/10 of the gate fall time for PMOS • More detailed estimation can be found in the design manuals of major foundries. An accurate estimation requires a calculation of the substrate current during the change of state. Quader&Hu et al. (1994)

12. Thermal Cycling of FE ASICs and FE Boards (for MicroBooNE) Cold motherboard with 12 ASICs populated. During extensive testing of ASICs and the motherboard, ASICs have gone through ~2200 immersions (of multiple chips) in LN2, the board has been immersed ~40 times without a single failure.

13. Future R&D Needs: Commercial FPGA and Regulators • FPGA candidates for cryogenic operation: ✔ ✗ ✔ ✔ ✔ ✗ ✗ List of FPGA screening tests: configuration (JTAG & Active Serial), embedded memory, high speed transceiver, I/O interface. • FPGA Lifetime: a standard method is to observe ring oscillator frequency under severe Vds stress [Wang et al. 2006], asdegradation of Ids leads to increased rise (propagation) time and reduced ring oscillator frequency. Needs further R&D. • Regulatorsfor cryogenic operation: 1.2 V and 2.5 V for FPGA, and 1.8 V for LAr ASICs. Selected 3 baseline devices, Globaltech GS2915L18F, TI TPS74201/74401, from a total of 19 devices (from ADI, Intersil, Linear, Maxim, National) tested. • Cold longtime experiment: Globaltech GS2915L18F tested >2 years;TI TPS74201/74401will start soon. Needs further R&D on lifetime.

14. Principal Findings and Design Guidelines 1.1. Two different measurements were used: accelerated lifetime measurement under severe electric field stress by the drain-source voltage (Vds), and a separate measurement of the substrate current (Isub) as a function of 1/Vds. The former verifies the canonical very steep slope of the inverse relation between the lifetime and the substrate current , , and the latter confirms that below a certain value of Vdsa lifetime margin of several orders of magnitude can be achieved for the cold electronics TPC readout. 1.2. Lifetime of digital circuits (ac operation) is extended by the inverse duty factor 1/(fckteff), compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequency needed for TPC. As an additional margin, Vdsmay be reduced by ~10%. 2. PC boards, packages, hybrids: Extremely low failure rate (incidence) in ATLAS LAr and NA48 LKr calorimeters, over a long time scale demonstrates on a large scale that surface mount circuit board technology withstands very well even multiple abrupt immersions in LN2 applied in board testing, and that the total failure incidence in continuous operation over time, ranging from 6 to13 years so far, is very low.

15. References (only a few key references, among numerous references on the subject, are given here): S. Li, J. Ma, G. De Geronimo, H. Chen, and V. Radeka, “LAr TPC electronics CMOS lifetime at 300 K and 77 K and reliability under thermal cycling,” IEEE Trans. Nuclear Science, vol. 60, no. 6, pp. 4737-4743, Dec. 2013. G. De Geronimo, A. D’Andragora, S. Li, N. Nambiar, S. Rescia, E. Vernon, H. Chen, F. Lanni, D. Makowiecki, V. Radeka, C. Thorn, and B. Yu, “Front-end ASIC for a liquid argon TPC,” IEEE Trans. Nuclear Science, vol. 58, no. 3, pp. 1376-1385, June 2011. J. R. Hoff, R. Aroar, J. D. Cressler, G. W. Deptuch, P. Gui, N. E. Lourenco, G. Wu, and R. J. Yarema, “Lifetime studies of 130 nm nMOStransisors intended for long-duration, cryogenic high-energy physics experiments,” IEEE Trans. Nuclear Science, vol. 59, no. 4, pp. 1757-1766, Aug. 2012. C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improvement”, IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, pp. 295-305, Feb. 1985. T. Chen, C. Zhu, L. Najafizadeh, B. Jun, A. Ahmed, R. Diestelhorst, G. Espinel, and J. D. Cressler,“CMOS reliability issues for emerging cryogenic Lunar electronics applications,” Solid-State Electronics, vol. 50, pp. 959-963, 2006. V.-H. Chan and J. E. Chung, “Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction”, IEEE Tran. Electron Devices, vol. 42, no. 5, pp. 957-962, May 1995. K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET’s”, IEEE Tran. Electron Devices, vol. ed-30, no. 8, pp. 871-876, Aug. 1983. P. K. Hurley, E. Sheehan, S. Moran, and A. Mathewson, “The impact of oxide degradation on the low frequency (1/f) noise behavior of p channel MOSFETs”, Microelectronics Reliability, vol. 36, no. 11/12, pp. 1679-1682, laar, “Hot-Ca1996.

16. 9. K. N. Quader, E. R. Minami, W.-J. Huang, P. K. Ko, and C. Hu, “Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits”, IEEE Journal of Solid-State Circuits, vol. sc-29, no. 3, pp. 253-262, March 1994. • 10. J. Wang, E. Olthof, and W. Metserrier Degradation Analysis Based on Ring Oscillators”, Microelectronics Reliability, 46, pp. 1858-1863, 2006. • 11. M. White and J.B. Bernstein, “Microelectronics Reliability: Physics-of -Failure Based Modeling and Lifetime Evaluation”, JPL Publication 08-5 2/08. Note: Manuals for each CMOS technology node provided by major foundries (e.g. IBM) are devoted to guidelines how to maximize transistor lifetime.

17. Backup Slides

18. Static Characteristics: Larger Sub-Threshold Slope at 77 K ID vs VDS ID vs VGS Some differences in saturation voltage, sub-threshold slope, transconductance

19. Noise: Lower White Noise and Lower PMOS 1/f Noise at 77K T = 300K T = 77K • lower white noise than at 300K • NMOS • comparable 1/f noise amplitude • Lorentzian packet • PMOS • lower 1/f noise amplitude • 1/f noise slope < 1 • comparable 1/f noise amplitude (i.e. comparable noise at 1 Hz) • different 1/f noise slope: PMOS > NMOS -> PMOS more advantageous for low-noise application.

20. 20 mm / 270 nm 0.3 1 48 mS 118mS 25 pF 28 pF • ID = 2 mA (3.6 mW) • W/L = 10 mm / 270 nm • IC 300K ≈ 0.4 IC 77K = 1.25 • gm_300K ≈ 45 mS gm_77K = 90 mS • Cg_300K ≈ 14 pF Cg_77K = 18 pF Input MOSFET Optimization for LAr TPC Analog Front-End ASIC Design input PMOSFET for 200pF detector electrodes (wires)! An improvement of ENC (~530 e- to ~420 e-) achieved using measured noise parameters. Selected size and operating point: original (simul. noise)vs. revised (meas. noise)

21. Lifetime vs1/Vds extracted from the stress measurements 1.7 x 107 yrs 8.9 x 104 yrs 5300 yrs PMOS shows ~2 orders of magnitude longer lifetime than NMOS.