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Chapter 6 CPU Design

Chapter 6 CPU Design. CPU Specification Very Simple CPU Relatively Simple CPU Simple CPU Shortcomings 8085 Microprocessor. Chapter Outline. Determine its intended applications Develop Instruction Set Architecture Design State Diagram. Specifying a CPU. CPU State Diagram. Fetch Decode

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Chapter 6 CPU Design

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  1. Chapter 6CPU Design

  2. CPU Specification Very Simple CPU Relatively Simple CPU Simple CPU Shortcomings 8085 Microprocessor Chapter Outline

  3. Determine its intended applications Develop Instruction Set Architecture Design State Diagram Specifying a CPU

  4. CPU State Diagram

  5. Fetch Decode Execute Instruction Cycle

  6. 64 x 8 memory Address pins A[5..0] Data Pins D[7..0] 8-bit Accumulator Very Simple CPU

  7. 6-bit Address Register AR 6-bit Program Counter PC 8-bit Data Register DR 2-bit Instruction Register IR Non-ISA Registers

  8. CPU outputs address on A[5..0] Delay for memory to perform its internal operations Read data from memory on D[7..0] Fetching Instructions from Memory

  9. FETCH1: AR  PC Fetch States

  10. Fetch States FETCH1: AR  PC FETCH2: DR  M

  11. Fetch States FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1

  12. Fetch States FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR[7..6], AR  DR[5..0]

  13. Fetch State Diagram

  14. Decoding Instructions

  15. ADD1: DR  M ADD2: AC  AC + DR Executing Instructions - ADD

  16. AND1: DR  M AND2: AC  AC ^ DR Executing Instructions - AND

  17. JMP1: PC  DR[5..0] Executing Instructions - JMP

  18. INC1: AC  AC + 1 Executing Instructions - INC

  19. FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR[7..6], AR  DR[5..0] ADD1: DR  M ADD2: AC  AC + DR AND1: DR  M AND2: AC  AC ^ DR JMP1: PC  DR[5..0] INC1: AC  AC + 1 Very Simple CPU Specification

  20. Very Simple CPU State Diagram

  21. Regroup operations by destination AR: ARPC; ARDR[5..0] PC: PCPC + 1; PCDR[5..0] DR: DRM IR: IRDR[7..6] AC: ACAC + DR; ACAC^DR; ACAC + 1 Establishing Data Paths

  22. Determine functions of each component AR, DR, and IR only load data PC and AC load and increment data Establishing Data Paths

  23. Preliminary Register Section

  24. AR only supplies data to memory Optimize Register Section

  25. Optimize Register Section • AR only supplies data to memory • IR only supplies data to control unit

  26. Optimize Register Section • AR only supplies data to memory • IR only supplies data to control unit • AC does not supply data to other registers

  27. Optimize Register Section • AR only supplies data to memory • IR only supplies data to control unit • AC does not supply data to other registers • Bus is 8-bits wide, but some registers have fewer bits

  28. Optimize Register Section • AR only supplies data to memory • IR only supplies data to control unit • AC does not supply data to other registers • Bus is 8-bits wide, but some registers have fewer bits • ALU needed to generate results

  29. Final Register Section

  30. Very Simple ALU

  31. Generic Hardwired Control Unit

  32. Assign FETCH1 to counter value 0 Control Unit Design Heuristics

  33. Control Unit Design Heuristics • Assign FETCH1 to counter value 0 • Assign sequential states to sequential values

  34. Control Unit Design Heuristics • Assign FETCH1 to counter value 0 • Assign sequential states to sequential values • Optimize assignment of values to first states of execute routines

  35. State Assignments

  36. State Assignments

  37. Very Simple CPU Control Unit

  38. Control Signals

  39. 0: ADD4 1: AND5 2: INC 3: JMP 0 4: 27H 5: 39H Design Verification

  40. 64K x 8 memory Address pins A[15..0] Data Pins D[7..0] 8-bit Accumulator AC 8-bit General Purpose Register R 1-bit Flag Register Z Relatively Simple CPU

  41. Instruction Set

  42. 16-bit Address Register AR 16-bit Program Counter PC 8-bit Data Register DR 8-bit Instruction Register IR 8-bit Temporary Register TR Non-ISA Registers

  43. FETCH1: AR  PC FETCH2: DR  M, PC  PC + 1 FETCH3: IR  DR, AR  PC Fetch Cycle

  44. Fetch and Decode Cycles

  45. NOP1: (no operation) NOP Execute Cycle

  46. LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC Execute Cycle

  47. LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1

  48. LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR

  49. LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR LDAC4: DR  M

  50. LDAC Execute Cycle LDAC1: DR  M, PC  PC + 1, AR  AR + 1 LDAC2: TR  DR, DR  M, PC  PC + 1 LDAC3: AR  DR,TR LDAC4: DR  M LDAC5: AC  DR

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