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Multiple Descriptor-Queues. We discover the role played by the MULR-bit (bit #18) in the Transmit Control Register. Our ‘igbe.c’ tool. We wrote this module as an aid for doing ‘debugging’ of our device-driver routines
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Multiple Descriptor-Queues We discover the role played by the MULR-bit (bit #18) in the Transmit Control Register
Our ‘igbe.c’ tool • We wrote this module as an aid for doing ‘debugging’ of our device-driver routines • It creates a pseudo-file that will show us the current values in significant registers • Already it has disclosed a ‘problem’ with our previous ‘txburst.c’ demonstation • Driver wrote 0x0103F0F8 into TCTL, but ‘/proc/igbe’ shows 0x1103F0F8 in TCTL
Transmit Control (0x0400) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R =0 R =0 R =0 MULR TXCSCMT UNO RTX RTLC R =0 SW XOFF COLD (upper 6-bits) (COLLISION DISTANCE) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COLD (lower 4-bits) (COLLISION DISTANCE) CT (COLLISION THRESHOLD) 0 ASDV SPEED I L O S S L U TBI mode P S P R =0 0 0 E N R =0 EN = Transmit Enable SWXOFF = Software XOFF Transmission PSP = Pad Short Packets RLTC = Retransmit on Late Collision CT = Collision Threshold (=0xF) UNORTX = Underrun No Re-Transmit COLD = Collision Distance (=0x3F) TXCSCMT = TxDescriptor Minimum Threshold MULR = Multiple Request Support We used 0x0103F0F8 in TCTL to setup the ‘transmit engine’ before enabling it 82573L
Twin Descriptor Queues TDBA0 Tx Desc Queue0 TDBA1 Tx Desc Queue1 TDH1 TDH0 TDT0 TDT1 = descriptor is ‘owned’ by device-driver = descriptor is ‘owned’ by network-controller
Tx Arbitration Count (0x3840) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED =0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED =0 0 E N A B L E RATIO I L O S R =0 S L U COUNT (must not be 0) TBI mode 0 0 ENABLE = Descriptor Enable (Always set to1) RATIO = Compensation Ratio (00=1/1, 01=1/2, 10=1/4, 11=1/8) 82573L