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Chapter 5

Chapter 5. Sequential Circuits: Flip-Flops and Counter By Taweesak Reungpeerakul. Contents. Introduction Latches Edge-Triggered Flip-Flops (ET-FFs) Operating Characteristics and Application Asynchronous Counter Synchronous Counter Cascaded Counters Counter Decoding

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Chapter 5

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  1. Chapter 5 Sequential Circuits: Flip-Flops and Counter By Taweesak Reungpeerakul 241-208 CH7

  2. Contents • Introduction • Latches • Edge-Triggered Flip-Flops (ET-FFs) • Operating Characteristics and Application • Asynchronous Counter • Synchronous Counter • Cascaded Counters • Counter Decoding • Counter Applications • Conclusions 241-208 CH7

  3. Contents • Basic Shift Register Functions • Serial In/Serial Out Shift Registers • Serial In/Parallel Out Shift Registers • Parallel In/Serial Out Shift Registers • Parallel Out/Parallel Out Shift Registers • Bidirectional Shift Registers • Shift Register Counters • Shift Register Applications • Conclusions 241-208 CH7

  4. Introduction Well, what u learned before is just one class of digital circuits. In fact we can classify into two main classes :- Output can depend on the past and present inputs/outputs. Output depends on the present input. 241-208 CH7

  5. Introduction (cont.) Synchronous VS Asynchronous • All state transitions are • controlled by a common clock • Changes in all variables occur • concurrently • State transitions occur independently • of any clock • Changes in all variables do not • necessarily occur concurrently 241-208 CH7

  6. S Q Q R Latches • A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory. • The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. R Q Q S NOR Active-HIGH Latch NAND Active-LOW Latch 241-208 CH7

  7. R R Q Q S S Q Q S-R Latch The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW. 0 0 1 Latch initially RESET Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. 0 1 0 0 1 0 Latch initially SET To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. 0 1 0 241-208 CH7

  8. Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. S R S To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Q Q R S-R Latch (cont.) The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. 1 1 0 Q Latch initially RESET 1 0 1 1 0 1 Q Latch initially SET 0 1 Never apply an active set and reset at the same time (invalid). 1 241-208 CH7

  9. Q Latch with Enable A gated latch is a variation on the basic latch. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. S Q EN Show the Q output with relation to the input signals. Assume Q starts LOW. Example R Solution Keep in mind that S and R are only active when EN is HIGH. S R EN Q 241-208 CH7

  10. Q Q D Latch The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D Q D Q EN EN A simple rule for the D latch is: Q follows D when the Enable is active. 241-208 CH7

  11. Truth Table of D Latch The truth table for the D latch summarizes its operation. If EN is LOW, then there is no change in the output and it is latched. 241-208 CH7

  12. Q Notice that the Enable is not active during these times, so the output is latched. Example Q D EN Determine the Q output for the D latch, given the inputs shown. 241-208 CH7

  13. Edge-Triggered Flip-Flops Circuit type: Synchronous bistable device Q:What is bistable ? A: Remain in one of two stable states until it receives a pulse (logic 1 signal) through one of its inputs, upon which it switches, or ‘flips’, over to the other state. 241-208 CH7

  14. Edge-Triggered Flip-Flops (cont.) • ET-FF characteristics: • 1-bit storage devices • Why? 1) Since outputs can be set to store either ‘0’ or ‘1’, depending on the inputs • 2) outputs retain their prescribed values (bistable prop.) • FF have 2 complimentary outputs (Q, Q) • Three main FF types: R-S, D-type, J-K • Changes state either at the positive or negative edge of the clock pulse 241-208 CH7

  15. Edge-Triggered Flip-Flops (cont.) The active edge can be positive or negative. Dynamic input indicator 241-208 CH7

  16. Q Edge-Triggered Flip-Flops (cont.) • More versatile than other FFs. • Has 2 inputs (J and K) and 2 outputs Q J CLK K Positive ET-J-K FF symbol 241-208 CH7

  17. Edge-Triggered Flip-Flops (cont.) 241-208 CH7

  18. Q Edge-Triggered Flip-Flops (cont.) Q J CLK K Positive ET-J-K FF truth table How comes ? 241-208 CH7

  19. Edge-Triggered Flip-Flops (cont.) Here is one example to test your understanding. Consider only positive-edged of the clock pulse 241-208 CH7

  20. Edge-Triggered Flip-Flops (cont.) One more example and try to figure out by yourself !! Set Toggle Set Latch CLK J K Q 241-208 CH7

  21. Q Edge-Triggered Flip-Flops (cont.) Asynchronous Preset and Clear inputs FF outputs are independent of the clock if either “Preset” or “Clear” is asserted. PRE Q J CLK K CLR 241-208 CH7

  22. PRE Q CLR Edge-Triggered Flip-Flops (cont.) Check by yourself for this example ! Latch Set Toggle Set Reset Toggle PRE CLK Q J J K Set CLK Reset K Q CLR 241-208 CH7

  23. FFs Operating Characteristics Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition. 50% point on triggering edge CLK CLK 50% point 50% point on HIGH-to- LOW transition of Q Q Q 50% point on LOW-to-HIGH transition of Q tPLH tPHL The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications. 241-208 CH7

  24. FFs Operating Characteristics (cont.) Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns. 50% point CLR 50% point PRE Q 50% point Q 50% point tPHL tPLH 241-208 CH7

  25. FFs Operating Characteristics (cont.) Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. D Setup time is the minimum time for the data to be present before the clock. CLK Set-up time, ts Hold time is the minimum time for the data to remain after the clock. D CLK Hold time, tH 241-208 CH7

  26. FFs Operating Characteristics (cont.) • Some other important characteristics are:- • Maximum clock frequency • Pulse widths • Power dissipation • Speed-power product 241-208 CH7

  27. FF Applications • Parallel data storage • Frequency division • Counter (will be illustrated in detail later on) 241-208 CH7

  28. Q FF Applications (cont.) Output lines Data storage Q0 Data is stored until the next clock pulse. Q1 PRE Q J Q2 Parallel data input lines CLK Q3 K Clock CLR Clear 241-208 CH7

  29. FF Applications (cont.) For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to continue to divide by two. HIGH HIGH One flip-flop will divide fin by 2, two flip-flops will divide fin by 4 (and so on). A side benefit of frequency division is that the output has an exact 50% duty cycle. QA QB fout J J fin CLK CLK K K fin Waveforms: fout 241-208 CH7

  30. Counter Counting in binary. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 LSB changes on every number. The next bit changes on every fourth number. The next bit changes on every other number. 241-208 CH8

  31. Counter (cont.) • Counter can be formed by connecting FFs together • Counter can be categorized into two cases, according to the ways they are clocked !! • Asynchronous counter (ripple counter) • Each FF formed counter do not change their states at the same time • Synchronous counter • Each FF in this counter is clocked concurrently. 241-208 CH8

  32. HIGH Q0 Q1 Q2 J0 J1 J2 CLK C C C Q0 Q1 K0 K1 K2 Asynchronous Counters Three bit asynchronous counter In an asynchronous counter, the clock is applied only to the first stage. Subsequent stages derive the clock from the previous stage. The three-bit asynchronous counter shown is typical. It uses J-K flip-flops in the toggle mode. Waveforms are on the following slide… 241-208 CH8

  33. Asynchronous Counters (cont.) Notice that the Q0 output is triggered on the leading edge of the clock signal. The following stage is triggered from Q0. The leading edge of Q0 is equivalent to the trailing edge of Q0. The resulting sequence is that of an 3-bit binary up counter. CLK Q0 Q1 Q2 241-208 CH8

  34. Asynchronous Counters (cont.) Propagation delay Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage. CLK Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. Q0 Q1 Q2 Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays. 241-208 CH8

  35. HIGH Q0 Q1 Q2 J0 J1 J2 CLK C C C Q0 Q1 K0 K1 K2 Asynchronous Counters (cont.) The modulus of a counter is the number of output states it goes through before returning its self back to zero. The maximum possible number of states (maximum modulus) of a counter is 2n Counter with 3 FFs count from 0-7 and called modulo-8 counter. Counters can be designed to have a number of states in their sequences <2n.This type of sequence is called a truncated sequence. 241-208 CH8

  36. HIGH Q3 Q0 Q1 Q2 J0 J1 J2 J3 CLK C C C C K0 K1 K2 K3 Asynchronous Counters (cont.) Asynchronous decade counter This counter uses partial decoding to recycle the count sequence to zero after the 1001 state (modulo-10 counter). CLR Use the output of NAND gate to clear input of the FFs 241-208 CH8

  37. Asynchronous Counters (cont.) Asynchronous decade counter (cont.) When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line. CLK Q0 Glitch Q1 Q2 Q3 CLR 241-208 CH8 Glitch

  38. Asynchronous Counters (cont.) The 74LS93A asynchronous counter The 74LS93A has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B. The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count. CLK B J0 J1 J2 J3 C C C C CLK A K0 K1 K2 K3 All J and K inputs are connected internally HIGH RO (1) RO (2) 241-208 CH8 Q3 Q0 Q1 Q2

  39. Synchronous Counters All flip-flops are clocked together with a common clock pulse. Trade small propagation delays with more circuitry to control states changes. Toggle mode 241-208 CH8

  40. Synchronous Counters (cont.) Timing diagram of 2-bit synchronous counter 241-208 CH8

  41. Synchronous Counters (cont.) 3-bit binary synchronous counter HIGH Q0 Q0Q1 Q0 Q1 Q2 J0 J1 J2 C C C K0 K1 K2 CLK Timing diagram of 3-bit synchronous counter 241-208 CH8

  42. Synchronous Counters (cont.) Analysis of synchronous counters (Tabular technique) 1. Put the counter in an arbitrary state; then determine the inputs for this state. HIGH Q0 Q0Q1 Q2 Q0 Q1 J0 J1 J2 2. Use the new inputs to determine the next state: Q2 and Q1 will latch and Q0 will toggle. C C C K0 K1 K2 3. Set up the next group of inputs from the current output. CLK Outputs Logic for inputs 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 4. Q2 will latch again but both Q1 and Q0 will toggle. 0 1 0 241-208 CH8

  43. Synchronous Counters (cont.) Analysis of synchronous counters (Tabular technique) Outputs Logic for inputs 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 At this points all states have been accounted for and the counter is ready to recycle… 241-208 CH8

  44. Synchronous Counters (cont.) A 4-bit synchronous binary counter The 4-bit binary counter has one more AND gate than the 3-bit counter just described. The shaded areas show where the AND gate outputs are HIGH causing the next FF to toggle. Q0 Q1 Q2 Q3 241-208 CH8

  45. Synchronous Counters (cont.) 4-bit synchronous decade counter With some additional logic, a binary counter can be converted to a BCD synchronous decade counter. After reaching the count 1001, the counter recycles to 0000. This gate detects 1001, and causes FF3 to toggle on the next clock pulse. FF0 toggles on every clock pulse. Thus, the count starts over at 0000. Q3 Q0 241-208 CH8

  46. Synchronous Counters (cont.) Waveforms for the decade counter: CLK Q0 Q1 Q2 Q3 241-208 CH8

  47. Synchronous Counters (cont.) A 4-bit synchronous binary counter in IC form The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two chip enables, and a ripple count output that signals when the count has reached the terminal count. Data inputs D0 D1 D2 D3 (Ripple Clock Output) goes high when count to state 15 CLR LOAD ENT RCO ENP CLK Both enable I/Ps Q0 Q1 Q2 Q3 241-208 CH8 Data outputs

  48. Synchronous Counters (cont.) CLR LOAD D0 D1 Data inputs D2 D3 CLK ENP ENT Q0 Q1 Data outputs Q2 Q3 RCO 12 13 14 15 0 1 2 241-208 CH8 Count Inhibit Clear Preset

  49. Down/ Q2 changes states when Q1&Q0=0 Down/ Q1 changes states when Q0=0 Always toggle, hence J0=K0 =1 Up/ Q2 changes states when Q1&Q0=1 Up/ Q1 changes states when Q0=1 Up/Down Synchronous Counters • Counting in either direction (also called a bi-directional counter) Says if u’d like to design a 3-bit up/down counter Up Q2 Q1 Q0 Down Clock pulse 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 241-208 CH8

  50. Up/Down Synchronous Counters (cont.) UP HIGH FF0 FF1 FF2 Q2 J0 J1 J2 Q0 Q1 UP/DOWN C C C Q0 Q1 Q2 K0 K1 K2 DOWN Q0.DOWN CLK Basic 3-bit up/down synchronous counter 241-208 CH8

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