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Commercial FPGAs: Altera Stratix Family

Commercial FPGAs: Altera Stratix Family. Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223. Notes on T hese Slides. Altera has disclosed the details of their devices both in online documentation and academic papers

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Commercial FPGAs: Altera Stratix Family

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  1. Commercial FPGAs: Altera Stratix Family Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223

  2. Notes on These Slides • Altera has disclosed the details of their devices both in online documentation and academic papers • The academic papers evaluate different design decisions and tradeoffs; the experiments are a bit too specialized for this course. • Please do not overly emphasize the experimentation in your studies

  3. The Stratix TM Routing and Logic Architecture D.M. Lewis, et al., International Symposium on FPGAs, 2003 Online documentation

  4. Altera Stratix FPGA

  5. Stratix Logic Element (LE)

  6. Register Feedback Mode

  7. Register Cascade (Shift Regs.)

  8. Logic Array Block (LAB)

  9. Directionally Biased Routing • Long vertical wires require power drivers • Fewer vertical wires • More rows than columns • More demand for horizontal wires

  10. The Stratix II Logic and Routing Architecture D.M. Lewis, et al., International Symposium on FPGAs, 2005 Online documentation

  11. Logic Array Block (LAB)

  12. Adaptive Logic Module (ALM)

  13. Adaptive Logic Module (ALM)

  14. Four ALM Operating Modes • Normal Mode • Extended LUT Mode • Arithmetic Mode • Shared Arithmetic Mode

  15. Normal Mode

  16. LUT Input Utilization

  17. Extended LUT Mode • Some 7-input logic functions

  18. Arithmetic Mode

  19. Arithmetic Mode ExampleR = (X < Y) ? Y : X Configure the LUTs to pass X through unmodified, and ignore the carry chain outputs • (X < Y) • Compute X-Y using the carry chain • Only look at the carry output • Use the carry output to select either X or Y accordingly

  20. Shared Arithmetic Mode (3-input Add)

  21. Register Chain (Shift Registers) • Separates logic and shift register functions • Cycle 1 • Combination logic • Cycles 2..k+1 • Shift by k • …

  22. ALM Benefits • Reduced LAB area by 2.6% compared to Stratix • 15% performance improvement • When shrinking from a 0.13um(Stratix) to 90nm (Stratix II) technology node • 51% performance improvement • 50% area decrease

  23. TriMatrix Embedded Memories

  24. M512 RAM Block Functions • 1-port RAM • 2-port RAM • FIFO • ROM • Shift Register 576 RAM bits (32 x 18), includes parity bits

  25. M4K RAM Block Functions • 1-port RAM • 2-port RAM • True 2-port RAM • FIFO • ROM • Shift Register 4,608 RAM bits (128 x 36), includes parity bits

  26. M-RAM Block Functions • 1-port RAM • 2-port RAM • True 2-port RAM • FIFO 589,824 RAM bits (4K x 144), includes parity bits

  27. MRAM LAB Interface

  28. DSP Blocks • Eight 9x9 multipliers • Four 18x18 multipliers • One 36x36 multiplier

  29. DSP BlockInternals Add/Sub/Accum Functions • Multiplier • Multiply-Accum • AB + CD • AB + CD + EF + GH

  30. DSP Block Interconnect Interface

  31. Architectural Enhancements in Stratix-IIITM and Stratix-IVTM D.M. Lewis, et al., International Symposium on FPGAs, 2009 Online documentation (Stratix III) Online documentation (Stratix IV)

  32. New Features • Programmable power management • LUT-RAM • LUT-Register Mode • Enhanced DSP Block

  33. Programmable Body Bias Control • Large regions • Less body bias control circuitry • Small regions • Fine-grained power mgmt

  34. Power Efficiency

  35. LUT-RAM y x • Idea • Use the SRAM bits as memory • Granularity is LAB-wide • What is needed? • Write capability • Signals for address and data for the write path SRAM SRAM SRAM SRAM

  36. LUT-RAM Architecture Supports one read + one write in a single cycle

  37. MLAB vs. LAB

  38. ALM LUT-Register Mode https://upload.wikimedia.org/wikipedia/commons/c/c6/R-S_mk2.gif

  39. ALM LUT-Register Mode

  40. DSP Block Capabilities • High-performance, power-optimized, fully registered and pipelined multiplication operations • Natively supported 9-bit, 12-bit, 18-bit, and 36-bit wordlengths • Natively supported 18-bit complex multiplications • Efficiently supported floating-point arithmetic formats (24-bit for single precision and 53-bit for double precision) • Signed and unsigned input support • Built-in addition, subtraction, and accumulation units to combine multiplication • results efficiently • Cascading 18-bit input bus to form tap-delay line for filtering applications • Cascading 44-bit output bus to propagate output results from one block to the next block without external logic support • Rich and flexible arithmetic rounding and saturation units • Efficient barrel shifter support • Loopback capability to support adaptive filtering

  41. DSP Block Overview

  42. Multiply-Add

  43. 4-Multiply Add w/Accumulation

  44. Cascading Output for FIR Filters

  45. Full DSP Block

  46. Half-DSP Block Architecture

  47. Four 9-bit Independent Half-DSP Multiplier Mode

  48. Three 12-bit Independent Half-DSP Multiplier Mode

  49. Two 18-bit Independent Half-DSP Multiplier Mode

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