Cognitive Radio Kit Tutorial

1. Cognitive Radio KitTutorial Khanh Le, Prasanthi Maddala and Ivan Seskar WINLAB, Rutgers University Date : June 20, 2012

2. Motivation • Challenges in Cognitive Radio (CR) and Dynamic Spectrum Access (DSA) techniques • No currently available widebandand real-time radio system for CR and DSA experimentation purpose • Complete Radio system design is a complicated and elaborated process • Solution to resolve this problem ? Yes, CRKIT Framework • With CRKIT Framework, we can abstract the lower level HW design complexities from users • Concentrate more on Creative side of the Wireless problems, less on Engineering Complexity

3. What is CRKIT Framework ? CRKIT HW Platform SW Platform ORBIT Integration Wideband Radio Flexible Baseband Embedded HOST PHY Layer Exp. Exp. Scalability FPGA- SoC Comm. APPs Radio APIs OMF • Baseband Processor : • FPGA-based off-the-shelf board • Multitude of high-speed IOs : GigE, USB, PCIe • Control up to 4 full-duplex wideband radios • FPGA-based System-on-Chip (FSoC) implementation CRKIT baseband with 4 stacked radios • Wideband Radio (WDR) Module : • Wideband : tunable range 300MHz to 7.5GHz • 25MHz bandwidth • 50Msps 12-bit ADC, 200Msps 12-bit DAC • 50us switch between frequencies Actual CogRadio with enclosure, 2 WDRs Baseband with 1 mounted radio

4. Why CRKIT Framework ? • Focus on Creativity, not Engineering Complexity : • Split Baseband into Static and Dynamic domains : • Static - Open-sourced System-on-Chip • (complex engineering problem) • Dynamic – Swappable Communication APPs • (creative problem) INNOVATIONCYCLE Focus on APP Development NOT complete Radio Abstract lower level design complexities from Users • FSoC Features • Access to lower level resources thru APIs • VITA radio transport protocol for radio control • Networking capable node • Support up to four different dynamic APPs • Library of Open-sourced Communication APPs • Static Framework utilization level < 15% for V5SX95, even less for newer technologies, for ex. Virtex7 . • Transparent to underlying FPGA technology. • Can be ported to future HW platforms and newer FPGA technologies. • Build Radio : • Non trivial effort • Substantial barrier to entry • Many engineering man-hours needed • Requires cross-disciplinary expertise Live system runs CRKIT= make real-time and wideband radio a viable solution for large scale experiments. CogRadio from RTS

5. FSoC Overview • FSoC currently consists of following major components : • Ethernet Port (static) • Gigabit Ethernet rate • frame synchronization • frame generation/formatting • Support Jumbo frames • Packet Processor (static) • Simple packet classification/forwarding scheme based on IP/UDP • Control packets -> Processor Core • Data packets -> APP • Support a subset of VITA Radio Transport protocol • Memory management for APP data • IP/VITA packet generation/formatting • Application (dynamic) • User specific designs e.g. simple QPSK/QAM, OFDM, FHSS, DSSS… • Support up to 4 APPs simultaneously (number of APPs is restricted by FPGA size) • APPs can be swapped as needed by users. APPs can either reside in RAM or downloadable through Ethernet port. • Will require partial reconfiguration • RF Port (static) • interfacing to DA/AD • RMAP Processor (static) • Sub-system interfacing and control • Address decoding • RF SPI Control • Processor Core (static) • 32-bit Softcore processor • interfacing to 32MB DRAM • interfacing to 16MB FLASH Three distinct data flows through system: 1) APP/Processor Core to outbound ethernet port 2) Inbound ethernet port to APP 3) Inbound ethernet port to Processor Core

6. CRKIT Transport Layers Application domain (dynamic) Framework Domain : Framework domain (static) • ETH Layer – Ethernet Physical layer only, no MAC. Only Ethernet frames with Broadcast MAC or matching destination MAC addresses are forwarded to IP layer. • IP Layer (Fast Path) – • Hardware based implementation • Only a subset of IP and UDP functions. • Fast track is reserved for APP data related traffic • Data IP packets are routed to the fast track based on specific UDP port number. • IP Layer (Slow Path) – • Software based implementation • Support TCP as this is done in SW e.g. processor core. • Slow track is reserved mostly for control related traffic : CRKit hardware configuration (register map access) and RF control. • Any IP packets with UDP port number not matching the fast track UDP port number will be routed to the slow track. • Note : for Address Resolution Protocol (ARP) the IP layer is bypassed, we parse the packets based on Ethernet frame Ethertype field. • VRT Layer – • VITA Radio Transport layer, only a subset of VITA standard is supported. • VRT layer is optional, bypass this layer if not used. • VRT useful to mux multiple radio streams to a single pipe, and demux at the other end. • Standardized radio packet types: 1) Data for signal data transmission, could be digitized I/Q samples. 2) Context for control information such as set frequency, power level, bandwidth and so forth. Application Domain : • User Specific Layer - since we are in the APP domain, users have their freedom to add any new layers they may wish. • Wireless PHY – again user specific implementation.

7. Inbound Packet Processing Flow PCORE CMD FORMAT Ethertype = 0x0800 - IPv4 0x0806 - ARP If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM. PortID Lookup Table • Forward ethernet payload if : • incoming MAC = dMAC • incoming MAC = Broadcast • Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000-1004) then forward UDP payload to VITA Receiver else forward packet to PCORE

8. Inbound Packet Processor RMAP For UDP Port 1000 Traffic (VITA) Registers visible to PCORE For non-VITA traffic UDP 1001 => P0 UDP 1002 => P1 UDP 1003 => P2 UDP 1004 => P3 StreamID lookup (direct-mapped) APP Identifier

9. Outbound Packet Processing Flow if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP) else Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP) endif Lookup using PortID dMAC/Ethertype from IP Processor VRT Receiver Lookup using PortID dMAC/Ethertype appended to IP/VITA data if (V == 1) then Enable VITA formatting else Disable VITA formatting endif

10. Outbound Packet Processor RMAP VITA enable flag IP enable flag VITA header IP header Lookup using PID Data/Context Lookup using PID StreamID Lookup Table MAC/IP Lookup Table

11. CRKIT Register Address Map Upper 4 MSBs : 0x0-0x1 : PCORE 0x2 : CRKIT Others : Unused 0x0 : CMN 0x1 : ETH 0x2 : PKT 0x4-0xB : APP 0xC : DAC IF 0xD : ADC IF INT SPI, LED DCM/CLOCK CE

12. CRKIT Programming Model Network HOST CRKIT CRKIT development Application development Java, C# C C GUI Algorithm Comm. APP Embedded SW System Debugging System Test CR DSA VHDL/ Verilog Mathworks Simulink IP Networking HW Configuration Host CMD Parsing DHCP/ARP Lookup Tables/ RF ETH/VITA

13. APP Development Flow MATLAB Simulink Flow Lookup Table Configuration RF Control dynamic Config. (ETH/VITA) initial config. Xilinx ISE Flow • Get IP address using DHCP • Discover HOST • Configure CRKIT hardware • Parse HOST commands CRKIT Flow

14. APP Simulink Development Environment Data Verification IO Validation Channel Model BMU MON APP RF LPBK I/Q data .txt files BMU DRV I/Q ETH .txt files Register Read/Write PCORE DRIVER Send X data packets CMD .txt file

15. APP Simulink Testbench

16. CRKIT Example – Rendezvous APPs

17. CRKIT Example – QPSK Transmitter

18. CRKIT Example – QPSK Receiver

19. CRKIT Example – FPGA Utilization

20. ORBIT Integration Actual SB6 with two CRKITs ORBIT SB6 OPEN TO ORBIT COMMUNITY !

21. Conclusion • CRKIT = Advanced Radio System enabling experimental research in CR and DSA techniques • Powerful combination of Wideband Radio and Flexible Baseband Processing • FSoC Static and Dynamic domain spaces • APP development for Creativity and Productivity => MATLAB/Simulink • Framework development for Engineering Complexity=> Traditional Hardware design flow • ORBIT Integration => User Friendliness Experience + Experimentation Scalability

22. Future Work • Extend APP library : OFDM-based waveform APP • Upgrade Static framework to support live loadable APPs from Network : • Clock Management • Run-time Reconfiguration • Port Linux to PCORE • Integrate CRKIT fully into ORBIT Management Framework • Upgrade current baseband board to newer and higher performance FPGA technologies