Topics

1. Topics • Basic fabrication steps. • Transistor structures. • Basic transistor behavior. • Latch up.

2. Fabrication services • Educational services: • U.S.: MOSIS • EC: EuroPractice • Taiwan: CIC • Japan: VDEC • Foundry = fabrication line for hire. • Foundries are major source of fab capacity today.

3. Fabrication processes • IC built on silicon substrate: • some structures diffused into substrate; • other structures built on top of substrate. • Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) • Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). • Silicon dioxide (SiO2) is insulator.

4. transistor via Simple cross section SiO2 metal3 metal2 metal1 poly substrate n+ n+ p+ substrate

5. Photolithography Mask patterns are put on wafer using photo-sensitive material:

6. Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub p-tub substrate

7. Process steps, cont’d. Pattern polysilicon before diffusion regions: gate oxide poly poly p-tub p-tub

8. Process steps, cont’d Add diffusions, performing self-masking: poly poly p-tub n+ n+ p-tub p+ p+

9. Process steps, cont’d Start adding metal layers: metal 1 metal 1 vias poly poly p-tub n+ n+ p-tub p+ p+

10. Transistor structure n-type transistor:

11. 0.25 micron transistor (Bell Labs) gate oxide silicide source/drain poly

12. Transistor layout n-type (tubs may vary): L w

13. Drain current characteristics

14. Drain current • Linear region (Vds < Vgs - Vt): • Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5Vds2) • Saturation region (Vds >= Vgs - Vt): • Id = 0.5k’ (W/L)(Vgs - Vt) 2

15. 0.5 m transconductances From a MOSIS process: • n-type: • kn’ = 73 A/V2 • Vtn = 0.7 V • p-type: • kp’ = 21 A/V2 • Vtp = -0.8 V

16. Current through a transistor Use 0.5 m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. • Vgs = 2V: Id = 0.5k’(W/L)(Vgs-Vt)2= 93 A • Vgs = 5V: Id = 1 mA

17. Basic transistor parasitics • Gate to substrate, also gate to source/drain. • Source/drain capacitance, resistance.

18. Basic transistor parasitics, cont’d • Gate capacitance Cg. Determined by active area. • Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. • Cgs = Col W • Gate/bulk overlap capacitance.

19. Latch-up • CMOS ICs have parastic silicon-controlled rectifiers (SCRs). • When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. • Early CMOS problem. Can be solved with proper circuit/layout structures.

20. Parasitic SCR circuit I-V behavior

21. Parasitic SCR structure

22. Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

23. Tub tie layout p+ metal (VDD) p-tub