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S 1 =A+B

+V. R. X. Y. C. B. Z. A. R. -V. Familia DL (Diode Logic). S 2 =X • Y. • Z. +C. S 1 =A+B. ?. S 2 =X • Y •(A+B+C). 2.0 1.5 1.0 0.5. V CC. R C. v O. Z. R B. 450. 450. 0.2 0.4 0.6 0.8 1.0. v i. V CC =3,6V. V CC =3,6V. 640. 640. Z.

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S 1 =A+B

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  1. +V R X Y C B Z A R -V Familia DL (Diode Logic) S2=X•Y •Z +C S1=A+B ? S2=X•Y•(A+B+C)

  2. 2.0 1.5 1.0 0.5 VCC RC vO Z RB 450 450 0.2 0.4 0.6 0.8 1.0 vi VCC=3,6V VCC=3,6V 640 640 Z Z 450 B C A 450 450 450 A C B Familia RTL (Resistor-Transistor Logic) =A’ A =(A+B+C)’ =(A+B+C)’

  3. VCC=5V VO 5.0 4.0 3.0 2.0 1.0 2K 2K =A’ Z A D1 D2 B B 20K C C VBB= -2V VOH (mín) = 2.6 V VCC=5V 2K 1,6K 2,15K VOL (máx) = 0.45 V Z =(A•B•C)’ A Q1 1.0 2.0 3.0 4.0 5.0 Vi D2 VIL (máx) = 1.0 V VIH (mín) = 1.9 V 5K Familia DTL (Diode -Transistor Logic) =(A•B•C)’

  4. 15.0 13.5 5.0 1.5 0 B B C C HTL VCC=15V VCC=5V 15K 2K 3K 1,6K DTL 12K 2,15K NMH NML Z =(A•B•C)’ Z =(A•B•C)’ 6,9V A A Q1 Q1 D2 0 1.5 5.0 6.5 7.5 8.5 13.5 15.0 5K 5K Familia HTL (High-Threshold Logic)

  5. VCC=5V vO R 1,6K 4K 5.0 4.0 3.0 2.0 1.0 Z Q2 A Q1 Q3 1K VCC=5V 130 1,6K 4K Q4 Q2 A Q1 Z 1.0 2.0 3.0 4.0 Q3 vI 1,2 1,35 5K Familia TTL (Transistor-Transistor Logic) Q 3,6 Q’ 2,6 P 0,2 0,5

  6. vO 4.0 3.0 2.0 1.0 VCC=5V Q 3,6 130 VCC=5V Q4 Q’ 2,4 IIL IOH 4K Q1 S Q3 E IIH IOL 0,4 P 0,2 vI 1.0 2.0 3.0 4.0 1,35 0,5 VI VO 2,0 0,8 N=0 3,6 N=10 2,4 VIH mín VOH mín 2,0 VOL máx 0,8 N=10 VIL máx 0,4 N=0 0,2 Familia TTL - Cargabilidad y Margen de Ruido N=0 N=10 NMH=0,4V NML=0,4V

  7. VCC=5V VCC=5V 130 130 1,6K 1,6K 4K 4K IB1H IB1L Q4 Q4 IC2 Q2 Q2 A A Q1 Q1 Z Z Q3 Q3 5K 5K vO vI 3.5 0.2 t t tpHL tpLH 15 5 vO ICC, mA t t Familia TTL – Disipación y Retardos Consumo Estático PD media 10 mW =0,7 mA =1 mA =2,5 mA Tiempo de propagación tpd medio 10 nseg. =8 nseg. =12 nseg.

  8. VCC=5V VCC=5V 130 130 4K 1,6K 1,6K 4K 4K Q4 Q4 Q2 Q2’ B D B Q2 C Q1’ Q1 Q1 Z Z B A VCC Q3 Q3 A 1,6K 4K 5K 5K 1K C A B B Z Z Z A A D B I Familia TTL – Compuertas Básicas =(A+B)’ =(AC+BD)’ =(A•B)’ I

  9. +5.0V 500 20K 40K +5.0V +5.0V +5.0V 12K 60 110 50 760 7K6 900 2,8K 24K 2,8K 4K 5K 1K 3K5 250 470 2K8 500 Familia TTL – Sub Familias High Speed TTL (alta velocidad) 54H /74H Low Power TTL (bajo consumo) 54L /74L 6 nseg. x 22 mW 33 nseg. x 1 mW Low Power Schotky TTL 54LS /74LS Schotky TTL 54S /74S 5 nseg. x 2 mW 3 nseg. x 20 mW

  10. VCC=masa B Z 300 290 300 Z’ A VBB = -1.175V Z Z’ 1,5K 2K 1,5K 2,30K RE 1,18K A B VEE= - 5,2 V Familia ECL (Emisor-Coupled Logic) Consumo Estático PD media =A+B 45 mW =(A+B)’ Tiempo de propagación tpd medio 1 nseg.

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