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Chapter 3 Henry Hexmoor Types of Logic Circuits

Combinational logic circuits: Outputs depend only on its current inputs. A combinational circuit may contain an arbitrary number of logic gates and inverters but no feedback loops. A feedback loop is a connection from the output of one gate to propagate back into the input of that same gate

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Chapter 3 Henry Hexmoor Types of Logic Circuits

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  1. Combinational logic circuits: Outputs depend only on its current inputs. A combinational circuit may contain an arbitrary number of logic gates and inverters but no feedback loops. A feedback loop is a connection from the output of one gate to propagate back into the input of that same gate The function of a combinational circuit represented by a logic diagram is formally described using logic expressions and truth tables. Sequential logic circuits: Outputs depend not only on the current inputs but also on the past sequences of inputs. Sequential logic circuits contain combinational logic in addition to memory elements formed with feedback loops. The behavior of sequential circuits is formally described with state transition tables and diagrams. Chapter 3Henry HexmoorTypes of Logic Circuits Henry Hexmoor

  2. Combinational Circuit Analysis: Start with a logic diagram of the circuit. Proceed to a formal description of the function of the circuit using truth tables or logic expressions. Combinational Circuit Synthesis: May start with an informal (possibly verbal) description of the function performed. A formal description of the circuit function in terms of a truth table or logic expression. The logic expression is manipulated using Boolean (or switching) algebra and optimized to minimize the number of gates needed, or to use specific type of gates. A logic diagram is generated based on the resulting logic expression. Henry Hexmoor

  3. The general structure of a sequential Circuit: Combinational logic + Memory Elements Combinational outputs Memory outputs Combinational logic Memory elements External inputs Sequential Circuits • Memory element: a device that can remember value indefinitely, • or change value on command from its inputs. • Examples: latches and flip-flops Henry Hexmoor

  4. A combinational logic circuit has: A set of m Boolean inputs, A set of n Boolean outputs, and n switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input values A block diagram: Combinatorial Logic Circuit m Boolean Inputs n Boolean Outputs Combinational Circuits Henry Hexmoor

  5. Integrated circuit (informally, a “chip”) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip. Terminology - Levels of chip integration SSI (small-scale integrated) - fewer than 10 gates MSI (medium-scale integrated) - 10 to 100 gates LSI (large-scale integrated) - 100 to thousands of gates VLSI (very large-scale integrated) - thousands to 100s of millions of gates Integrated Circuits (IC) Henry Hexmoor

  6. To control the complexity of the function mapping inputs to outputs: Decompose the function into smaller pieces called blocks Decompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enough Any block not decomposed is called a primitive block The collection of all blocks including the decomposed ones is a hierarchy Example: 9-input parity tree (see next slide) Top Level: 9 inputs, one output 2nd Level: Four 3-bit odd parity trees in two levels 3rd Level: Two 2-bit exclusive-OR functions Primitives: Four 2-input NAND gates Design requires 4 X 2 X 4 = 32 2-input NAND gates Hierarchical Design Henry Hexmoor

  7. Hierarchy for Parity Tree Example X 0 X 1 X 2 9-Input X 3 odd X Z O 4 X function 5 X X A 6 0 0 3-Input X 7 odd A X B X 1 8 O 1 function A X (a) Symbol for circuit 2 2 X A A 3 0 0 3-Input 3-Input odd odd A A X B Z B 1 1 4 O O O function function A A X 2 2 5 X A 6 0 3-Input odd A X B 1 7 O function A X 2 8 (b) Circuit as interconnected 3-input odd function blocks A 0 A B 1 O A 2 (c) 3-input odd function circuit as interconnected exclusive-OR blocks Henry Hexmoor (d) Exclusive-OR block as interconnected NANDs

  8. Whenever possible, we try to decompose a complex design into common, reusable function blocks These blocks are verified and well-documented placed in libraries for future use Representative Computer-Aided Design Tools: Schematic Capture Logic Simulators Timing Verifiers Hardware Description Languages Verilog and VHDL Logic Synthesizers Integrated Circuit Layout Reusable Functions and CAD Henry Hexmoor

  9. A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks Designs usually proceed from both directions simultaneously Top-down design answers: What are we building? Bottom-up design answers: How do we build it? Top-down controls complexity while bottom-up focuses on the details Top-Down versus Bottom-Up Design Henry Hexmoor

  10. Specific gate implementation technologies are characterized by the following parameters: Fan-in – the number of inputs available on a gate Fan-out – the number of standard loads driven by a gate output Logic Levels – the signal value ranges for 1 and 0 on the inputs and 1 and 0 on the outputs (see Figure 1-1) Noise Margin – the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output Cost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit Propagation Delay – The time required for a change in the value of a signal to propagate from an input to an output Power Dissipation – the amount of power drawn from the power supply and consumed by the gate Technology Parameters Henry Hexmoor

  11. Propagation delay is the time for a change on an input of a gate to propagate to the output. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low (tPHL) and low-to-high (tPLH) output signal changes may have different propagation delays. High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input. An HL input transition causes: an LH output transition if the gate inverts and an HL output transition if the gate does not invert. Propagation Delay Henry Hexmoor

  12. Propagation delays measured at the midpoint between the L and H values What is the expression for the tPHL delay for: a string of n identical buffers? a string of n identical inverters? Propagation Delay (continued) Henry Hexmoor

  13. Transport delay - a change in the output in response to a change on the inputs occurs after a fixed specified delay rejection time is a specified value no larger than the propagation delay and it is often equal to it. (page 99) Inertial delay - similar to transport delay, except that if the input changes such that the output is to change twice in a time interval less than the rejection time, the output changes do not occur. Models typical electronic circuit behavior, namely, rejects narrow “pulses” on the outputs Delay Models Henry Hexmoor

  14. In an integrated circuit: The cost of a gate is proportional to the chip area occupied by the gate The gate area is roughly proportional to the number and size of the transistors and the amount of wiring connecting them Ignoring the wiring area, the gate area is roughly proportional to the gate input count So gate input count is a rough measure of gate cost If the actual chip layout area occupied by the gate is known, it is a far more accurate measure Cost Henry Hexmoor

  15. HDL – Hardware Description Languages allow rigidly defined language to represent logic circuits. • AHDL – Altera Hardware Description Language. • VHDL – Very High Speed Integrated circuit Hardware Description Language. • Developed by DoD • Standardized by IEEE • Widely used to translate designs into bit patterns that program actual devices. Hardware Description Languages3-1 OR Gate A Henry Hexmoor

  16. Boolean Description Using VHDL Example defines an AND gate. The keyword ENTITY names the circuit block, in this case: and_gate The keyword PORT defines the inputs and outputs. The keyword ARCHITECTURE describes the operation inside the block. The BEGIN and END contain a description of the operation HDL Format and Syntax Henry Hexmoor

  17. Specification: the circuit functions • Formulation: truth table or I/O mapping • Optimization: draw logic diagrams • Technology Mapping: map logic components to available components • Verification: correctness check • See Examples 3-2, 3-3, 3-4 Design Procedure3-3 Henry Hexmoor

  18. Specification Write a specification for the circuit if one is not already available Formulation Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification Optimization Apply 2-level and multiple-level optimization Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters Design Procedure Henry Hexmoor

  19. Technology Mapping Map the logic diagram or netlist to the implementation technology selected Verification Verify the correctness of the final design Design Procedure Henry Hexmoor

  20. Intentionally left blank Henry Hexmoor

  21. Specification BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word Implementation: multiple-level circuit NAND gates (including inverters) Design Example 3-2 Henry Hexmoor

  22. Formulation Conversion of 4-bit codes can be most easily formulated by a truth table Variables- BCD: A,B,C,D Variables- Excess-3 W,X,Y,Z Don’t Cares- BCD 1010 to 1111 Design Example (continued) Henry Hexmoor

  23. Optimization 2-level usingK-maps W = A + BC + BD X = C + D + B Y = CD + Z = C C z y 1 1 1 1 0 1 3 2 0 1 3 2 1 1 1 1 4 5 7 6 4 5 7 6 B B X X X X X X X X 12 13 15 14 12 13 15 14 A A 1 X X 1 X X 8 9 11 10 8 9 11 10 D D D D x C C w 1 1 1 0 1 3 2 0 1 3 2 1 1 1 1 4 5 7 6 4 5 7 6 B B X X X X X X X X 12 13 15 14 12 13 15 14 A A 1 X X 1 1 X X 8 9 11 10 8 9 11 10 C B D B C D D Design Example (continued) Henry Hexmoor

  24. Optimization (continued) Multiple-level using transformationsT1 = C + DW = A + BT1X = T1 + BY = CD + Z = An additional extraction not shown in the text since it uses a Boolean transformation: ( = C + D = ): W = A + BT1X = T1 + B Y = CD + Z = B B C D D D D D C T1 T1 T1 C Design Example (continued) Henry Hexmoor

  25. Technology Mapping: page 107 – 3rd ed. Mapping with a library containing inverters and 2-input NAND, 2-input NOR, and 2-2 AOI gates A W B X Y C D Z Design Example (continued) Henry Hexmoor

  26. Specification A BCD-to-seven-segment-decoder is a combinational circuit that accepts a decimal digit in BCD and generates the appropriate output for the selection of segments that display the decimal digit. Each digit is formed from 7 segments, each consisting of 1 LED that can be illuminated by digital signals. Design Example: BCD to BCD-to-Seven-Segment Decoder Henry Hexmoor

  27. f b g e c d • 2. Formulation (Truth table)To display the input BCD digit: • Which segment(s) should illuminate (be turned on)? • Which segment(s) should not illuminate (be turned off)? Henry Hexmoor

  28. Optimization:Boolean Function for each output • a=? b=? c=? d=? • e=? f=? g=? • Draw the logic diagram Henry Hexmoor

  29. Technology Mapping • Custom design • Cell design: reuse • Gate array: VLSI fabrication Henry Hexmoor

  30. Full custom - the entire design of the chip down to the smallest detail of the layout is performed Expensive Justifiable only for dense, fast chips with high sales volume Standard cell - blocks have been design ahead of time or as part of previous designs Intermediate cost Less density and speed compared to full custom Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a design Lowest cost Less density compared to full custom and standard cell Chip Design Styles Henry Hexmoor

  31. Cell - a pre-designed primitive block Cell library - a collection of cells available for design using a particular implementation technology Cell characterization - a detailed specification of a cell for use by a designer - often based on actual cell design and fabrication and measured values Cells are used for gate array, standard cell, and in some cases, full custom chip design Cell Libraries Henry Hexmoor

  32. Typical Typical Input-to- Basic Cell Cell Normalized Input Output Function Name Schematic Area Load Delay Templates 0.04 Inverter 1.00 1.00 0.012 SL 1 3 0.05 2NAND 1.25 1.00 0.014 SL 1 3 0.06 2NOR 1.25 1.00 0.018 SL 1 3 0.07 2-2 AOI 2.25 0.95 0.019 SL 1 3 Example Cell Library Henry Hexmoor

  33. Manual Logic Analysis Find the truth table or Boolean equations for the final circuit Compare the final circuit truth table with the specified truth table, or Show that the Boolean equations for the final circuit are equal to the specified Boolean equations Simulation Simulate the final circuit (or its netlist, possibly written as an HDL) and the specified truth table, equations, or HDL description using test input values that fully validate correctness. The obvious test for a combinational circuit is application of all possible “care” input combinations from the specification Basic Verification Methods Henry Hexmoor

  34. Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates Programmable Array Logic (PAL)Ò - a programmable array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) - a programmable array of AND gates feeding a programmable array of OR gates. Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) - complex enough to be called “architectures” - See VLSI Programmable Logic Devices reading supplement Programmable Configurations Henry Hexmoor PAL is a registered trademark of Lattice Semiconductor Corp.

  35. ROM, PAL and PLA Configurations Fixed Programmable Programmable Inputs Outputs AND array Connections OR array (decoder) (a) Programmable read-only memory (PROM) Programmable Programmable Fixed Inputs Outputs Connections AND array OR array (b) Programmable array logic (PAL) device Programmable Programmable Programmable Programmable Outputs Inputs Connections Connections AND array OR array (c) Programmable logic array (PLA) device Henry Hexmoor

  36. Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: N input lines, M output lines, and 2N decoded minterms. Fixed AND array with 2N outputs implementing all N-literal minterms. Programmable OR Array with M outputs lines to form up to M sum of minterm expressions. A program for a ROM or PROM is simply a multiple-output truth table If a 1 entry, a connection is made to the corresponding minterm for the corresponding output If a 0, no connection is made Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names! Read Only Memory Henry Hexmoor

  37. Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a“decoder” with 3 inputs and 8outputs implementing minterms. The programmable "OR“array uses a single line torepresent all inputs to anOR gate. An “X” in thearray corresponds to attaching theminterm to the OR Read Example: For input (A2,A1,A0)= 011, output is (F3,F2,F1,F0 ) = 0011. What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)? X X X D7 D6 X X D5 X D4 D3 A2 A X D2 X X B A1 D1 X A0 D0 C F0 F2 F1 F3 Read Only Memory Example Henry Hexmoor

  38. The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. Disadvantage ROM guaranteed to implement any M functions of Ninputs. PAL may have too few inputs to the OR gates. Advantages For given internal complexity, a PAL can have larger N and M Some PALs have outputs that can be complemented, adding POS functions No multilevel circuit implementations in ROM (without external connections from output to input). PAL hasoutputs from OR terms as internal inputs to all ANDterms, making implementation of multi-level circuits easier. Programmable Array Logic (PAL) Henry Hexmoor

  39. Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs. Advantages A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required  A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL Ors Some PLAs have outputs that can be complemented, adding POS functions Disadvantage Often, the product term count limits the application of a PLA. Two-level multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA. Programmable Logic Array (PLA) Henry Hexmoor

  40. 1. A majority function has an output value of 1 if there are more 1’s than 0’s on its inputs. The output is 0 otherwise. Design a three-input majority function. 3-10 2. design a circuit with a 4-bit BCD input A, B, C, D that produces an output W, X, Y, Z that is equal to the input + 6 in binary. For example 9(1001) + 6 (0110) = 15 (1111). 3-17 HW 3 Henry Hexmoor

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