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C HAPTER 5 D IGITAL CMOS L OGIC C IRCUITS

C HAPTER 5 D IGITAL CMOS L OGIC C IRCUITS. C HUN -L UNG H SU ICDT L AB ., D EPT . EE., NDHU. O UTLINE An Overview Logic-Circuit Characterization Noise Margin Propagation Delay Power Dissipation Delay-Power Product Silicon Area Fan-in & Fan-out CMOS Logic Circuits

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C HAPTER 5 D IGITAL CMOS L OGIC C IRCUITS

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  1. CHAPTER 5DIGITAL CMOS LOGIC CIRCUITS CHUN-LUNG HSU ICDT LAB., DEPT. EE., NDHU

  2. OUTLINE • An Overview • Logic-Circuit Characterization • Noise Margin • Propagation Delay • Power Dissipation • Delay-Power Product • Silicon Area • Fan-in & Fan-out • CMOS Logic Circuits • Transistor Sizing • Pseudo-NMOS Logic Circuits • Pass-Transistor Logic Circuits

  3. CMOS enable extremely high levels of integration of both logic and memory circuits. AN OVERVIEW • CMOS is by far the most popular technology for the implementation of digital systems. • Small size • Ease of fabrication • Low power dissipation • CMOS Digital IC technologies and logic-circuit families Complementary CMOS Pseudo-NMOS Pass-transistor logic Dynamic logic

  4. AN OVERVIEW • Some of the reasons for CMOS displacing bipolar technology in digital applications are listed as follows. • CMOS logic circuits dissipate much less power --- low power consumption. • The high input impedance of the MOS transistor allows the designer to use charge storage as a means for the temporary storage of information in both logic and memory circuits --- as storage element or no load effect. • The feature size (i.e., minimum channel length) of the MOS transistor has decreased dramatically over the year --- smaller feature size. • TSMC --- 0.35 um, 0.25 um, 0.18 um, 0.13 um • UMC --- 0.5 um • Some recently reported designs utilizing channel lengths as short as 0.06 um. This permits very tight circuit packing and, corresponding, very high levels of integration.

  5. Vin Vout Vout Vout Vin Vin NMOS + Enh. load NMOS + Dep. load NMOS + PMOS  CMOS LOGIC-CIRCUIT CHARACTERIZATION • The following parameters are usually used to characterize the operation and performance of a logic-circuit family. • The static operation of a logic-circuit family is characterized by the voltage transfer characteristic (VTC) of its basic inverter. Noise Margins Propagation Delay Power Dissipation Delay-Power Product Silicon Area Fan-in & Fan-out

  6. Vout VDD A II I III ID2 + VGD2 + + Q1 : Off Q2 : Sat. Q1 : Sat. Q2 : Sat. Q1 : Linear Q2 : Sat. - Q2 VDS1 VDS2 Vout - - VTC Vin Vin Switch Amplifier Switch Q1 + ID1 B VGS1 - Vt1 LOGIC-CIRCUIT CHARACTERIZATION • For example --- NMOS + Enhancement load • Vin = VGS1 • Vout = VDD – VDS2 = VDS1 • ID1 = ID2 • VGD2 = 0 Q2 is operated in saturation (pinch-off) region always. VDD – Vt2

  7. Slope = -1 Slope = -1 Vout VOH VDD – Vt2 Vout VTC Vin Vin VOL NMOS + Enh. load Vt1 VIH VIL LOGIC-CIRCUIT CHARACTERIZATION • Noise Margins • Minimum HIGH output voltage : VOH = VDD – Vt2 • Maximum LOW output voltage : VOL = ; when Vin = VOH • Minimum HIGH input voltage : VIH = ___, when dVout / dVin = -1 • Maximum LOW input voltage : VIL = ___, when dVout / dVin = -1 VOH

  8. Vout VOH Slope = -1 VDD – Vt2 Vout VTC Vin Vin Slope = -1 VOL NMOS + Enh. load VOH VIH VIL Vt1 LOGIC-CIRCUIT CHARACTERIZATION • Noise Margins • The robustness of a logic-circuit family is determined by its ability to reject noise, and thus by the noise margins NMH and NML. NMH = VOH - VIH NML = VIL - VOL

  9. Vout VOH = 5 – 1 = 4 VDD – Vt2 Slope = -1 5 5 How much noise margins are perfect ? Slope = -1 VOL = 0.8 4 2.8 Vin VOH = 4 1.8 VIL = 1.8 VIH = 2.8 0.8 0 0 LOGIC-CIRCUIT CHARACTERIZATION • Noise Margins • For example : NMH = 4 – 2.8 = 1.2 V ; NML = 1.8 – 0.8 = 1 V • How much noise can a gate input see before it does not recognize the input ?

  10. Vout I II VDD VDD III Qp + Vout Vin VSDP - IV IDP V + Qn Vin VSGP + - VDD VDSN Vtn - VTC + IDN VGSN - LOGIC-CIRCUIT CHARACTERIZATION • The noise margins in “NMOS + Ehn. Load” circuit are not suitable for digital circuit, since the voltages VOH and VOL can’t reach VDD and 0, respectively. • Another example : CMOS circuit • Vin = VGSN = VDD - VSGP • Vout = VDD – VSDP = VDSN • IDN = IDP Qn Off, Qp Linear Qn Sat., Qp Linear Qn Sat., Qp Sat. Qn Linear, Qp Sat. Qn Linear, Qp Off

  11. Ideal Switch Ideal Switch Vout I Circuit VDD VTC Operating Modes II VDD Qn Qp Qp Forbid region for CMOS logic I CutOff Linear Vin Digital Circuit Vout III II Saturation Linear III Saturation Saturation Qn Amplifier IV Linear Saturation IV V Vin V Linear CutOff Digital Circuit VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • CMOS circuit Region I • The ideal transistor switch model is valid in this region.

  12. Vout I Circuit VDD VTC II VDD Operating Modes Qp Qn Qp Vin Vout III I CutOff Linear Qn II Saturation Linear IV V III Saturation Saturation Vin IV Linear Saturation VDD Vtn V Linear CutOff LOGIC-CIRCUIT CHARACTERIZATION • CMOS circuit Region II • The physical transistor switch model is valid in this region.

  13. Vout I Circuit VDD VTC Operating Modes II VDD Qn Qp Qp I CutOff Linear Vin Vout III II Saturation Linear III Saturation Saturation Qn IV Linear Saturation IV V Vin V Linear CutOff VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • CMOS circuit Region III • The circuitis operated as an amplifier.

  14. Vout I Circuit VDD VTC Operating Modes II VDD Qn Qp Qp I CutOff Linear Vin Vout III II Saturation Linear III Saturation Saturation Qn IV Linear Saturation IV V Vin V Linear CutOff VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • CMOS circuit Region IV • The physical transistor switch model is valid in this region.

  15. Vout I Circuit VDD VTC Operating Modes II VDD Qn Qp Qp I CutOff Linear Vin Vout III II Saturation Linear III Saturation Saturation Qn IV Linear Saturation IV V Vin V Linear CutOff VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • CMOS circuit Region V • The ideal transistor switch model is valid in this region.

  16. If the parameter kn = kp& Vtn = Vtp Vout I II VDD VDD III Qp + Vout Vin VSDP - IV IDP V + Qn Vin VSGP + - VDD VDSN Vtn - VTC Circuit + IDN VGSN - Vth LOGIC-CIRCUIT CHARACTERIZATION • CMOS circuit --- threshold voltage Vth= VDD/2 An ideal inverter is one for which NMH = NML = VDD/2

  17. Vout I II VDD Slope = -1 III VOH = VDD and VOL = 0 Strong “H” and “L” IV V Vin Slope = -1 VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • How to determine the noise margins in a CMOS inverter ? • Minimum HIGH output voltage : VOH = VDD • Maximum LOW output voltage : VOL = 0, when Vin = VOH • Maximum LOW input voltage : VIL = ___, when dvout / dvin = -1 • Minimum HIGH input voltage : VIH = ___, when dvout / dvin = -1 VOH VOL VIH VIL

  18. Vout II I VDD Slope = -1 VOH III IV Slope = -1 V Vin VDD Vtn VIL VIH VOL 1 LOGIC-CIRCUIT CHARACTERIZATION • How much noise margins of the CMOS circuit, if the inverter threshold is at VDD/2. • Using regions IV and II to find the values of VIH and VIL. Region IV : Qn in Linear & Qp in Sat. VOH = VDD VOL = 0 VIH = ? VIL = ? VI = VIH

  19. Vout II I VDD Slope = -1 VOH III IV Slope = -1 V Vin VDD Vtn VIL VIH VOL 2 LOGIC-CIRCUIT CHARACTERIZATION • How much noise margins of the CMOS circuit, if the inverter threshold is at VDD/2. • Using regions IV and II to find the values of VIH and VIL. Region IV : Qn in Linear & Qp in Sat. VOH = VDD VOL = 0 VIH = ? VIL = ? VI = VIH when dVO/dVI = -1

  20. Vout II I VDD Slope = -1 VOH III IV Slope = -1 V Vin VDD Vtn VIL VIH VOL 1 2 LOGIC-CIRCUIT CHARACTERIZATION • How much noise margins of the CMOS circuit, if the inverter threshold is at VDD/2. • Using regions IV and II to find the values of VIH and VIL. Region IV : Qn in Linear & Qp in Sat. VOH = VDD VOL = 0 VIH = ? VIL = ?

  21. Vout II I VDD Slope = -1 VOH III IV Slope = -1 V Vin VDD Vtn VIL VIH VOL LOGIC-CIRCUIT CHARACTERIZATION • How much noise margins of the CMOS circuit, if the inverter threshold is at VDD/2. • Using regions IV and II to find the values of VIH and VIL. Region II : Qn in Sat. & Qp in Linear VOH = VDD VOL = 0 VIH = ? VIL = ? Using the same method as VIH to find VIL, however, it’s so complex.

  22. Vout II I VDD Slope = -1 VOH III IV Slope = -1 V Vin VDD Vtn VIL VIH VOL Vth =(1/2) VDD LOGIC-CIRCUIT CHARACTERIZATION • How much noise margins of the CMOS circuit, if the inverter threshold is at VDD/2. • Using regions IV and II to find the values of VIH and VIL. • We can use the symmetrical relation to find the value of VIL. • That is, VOH = VDD VOL = 0 VIH = ? VIL = ?

  23. LOGIC-CIRCUIT CHARACTERIZATION • How much noise margins of the CMOS circuit, if the inverter threshold is at VDD/2. • NMH = VOH – VIH = 1/8 (3VDD + 2Vt) • NML = VIL – VOL = 1/8 (3VDD + 2Vt) • Example : For a ideal CMOS inverter employing a 3.3-V supply and the voltages Vtn =｜Vtp︱ = 1V, please sketch the VTC and find the values of VOH, VIH, VIL, VOL, NMH, and NML. Also, calculate the output voltages at the demarcation points between the transient regions II, III, and IV. VOH = VDD VIH = 1/8 (5VDD – 2Vt) VIL = 1/8 (3VDD + 2Vt) VOL = 0

  24. Vout VOH II I VDD III IV V Vin VDD Vtn VIL VIH VOL VO1 VO2 Vth LOGIC-CIRCUIT CHARACTERIZATION • Example : For a ideal CMOS inverter employing a 3.3-V supply and the voltages Vtn =｜Vtp︱ = 1V, please sketch the VTC and find the values of Vth, VOH, VIH, VIL, VOL, NMH, and NML. Also, calculate the output voltages at the demarcation points between the transient regions II, III, and IV. • Vth = (1/2)VDD = 1.65 V • VOH = VDD = 3.3 V • VOL = 0 V • VIH = 1/8 (5VDD – 2Vt) = 1.8125 V • VIL = 1/8 (3VDD + 2Vt) = 1.4875 V • NMH = NML = 1/8 (3VDD + 2Vt) = 1.4875 V • VO1 = (1/2)VDD + Vt = 2.65 V • VO2 = (1/2)VDD – Vt = 0.65 V Solutions

  25. VDD Vout Qp I II VDD Vin Vout VO1 Qn III VO2 IV V Vin Vth VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • Example : For a CMOS inverter employing a 5-V supply and un = 600 cm-square/V-sec, up = 250 cm-square/V-sec, (W/L)n = 1, (W/L)p = 2, Vtn = |Vtp| = 0.8 V. Please Determine the values of Vth and the output voltages at the demarcation points between the transient regions II, III, and IV. • For region III, Qn& Qp are both operated in saturation. Solutions

  26. VDD = 5 un = 250 (W/L)n = 2 Vtp = 0.8 un = 600 (W/L)n = 1 Vtn = 0.8 VDD Vout Qp I II VDD Vin Vout VO1 Qn III If Qn& Qp are completely matched, then Vth = VDD/2 = 2.5 V. VO2 IV V Vin Vth VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • Example : • Determine the values of Vth. Solutions

  27. VDD = 5 un = 250 (W/L)n = 2 Vtp = 0.8 un = 600 (W/L)n = 1 Vtn = 0.8 VDD Vout Qp I II VDD Vin C B Vout IDn = IDp VO1 Qn Qn Qp C B III VO2 IV V Vin Vin Vth VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • Example : • Determine the values of Vo1. At B point, Qp is operated in the pinch-off point Solutions

  28. VDD = 5 un = 250 (W/L)n = 2 Vtp = 0.8 un = 600 (W/L)n = 1 Vtn = 0.8 VDD Vout Qp I II VDD Vin C B Vout IDn = IDp VO1 Qn Qn Qp C B III VO2 IV V Vin Vin Vth VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • Example : • Determine the values of Vo2. At C point, Qn is operated in the pinch-off point Solutions

  29. 50% The shorter the propagation delay, the higher the speed at which logic-circuit family can be operated. Vi Time Vo 50% Time tpHL = tpdf tpLH = tpdr LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • The dynamic performance of a logic-circuit family is characterized by the propagation delay of its basic inverter. • Propagation delay time,tpd : maximum time from the input crossing 50% to the output crossing 50%. tpd = 1/2 (tpHL + tpLH)

  30. Note that, during tPLH or tPHL, the output of the first inverter changes from 0 to VDD/2 or from VDD to VDD/2, respectively. Thus, we wish to replace all the capacitances attached to the inverter output node with a single capacitance C connected between the output node and ground. LOGIC-CIRCUIT CHARACTERIZATION • Dynamic operation • The propagation delay of the inverter is usually determined under the condition that is driving an identical inverter. • Circuit for analyzing the propagation delay of the inverter formed by Q1& Q2, which is driving an identical formed by Q3& Q4.

  31. Replace all the capacitances to single capacitance C at the output node. LOGIC-CIRCUIT CHARACTERIZATION • Dynamic operation • C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw The Cgd1 (Cgd2) can be replaced by an equivalent capacitance between the output node and ground of 2Cgd1 (2Cgd2). K = Vo / Vi = -1 Miller Effect, Cgd (1 – 1/K)

  32. Replace all the capacitances to single capacitance C at the output node. LOGIC-CIRCUIT CHARACTERIZATION • Dynamic operation • C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw Each of Cdb1 and Cdb2 has a terminal at a constant voltage. Thus, Cdb1 and Cdb2 can be replaced with equal capacitances between the output node and ground.

  33. Replace all the capacitances to single capacitance C at the output node. Carea Cfringe Cfringe fF / um fF / um LOGIC-CIRCUIT CHARACTERIZATION • Dynamic operation • C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw Cg = Cox x W x L + Cgsov x W + Cgdov x W fF / um-square

  34. VDD Vout t = 0 I VDD II III Vin Vout IV VDD V Vin CL Vtn VDD VDD/2 Vout Vin CL iDN LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • It is based on computing an average value for the discharge current iDN during the interval t = 0 to t = tPHL. • At t = 0, NMOS will be operated in saturation. tPHL

  35. VDD Vout I VDD II III Vin t = tPHL Vout IV VDD V Vin CL Vtn VDD VDD/2 Vout Vin CL iDN LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • It is based on computing an average value for the discharge current iDN during the interval t = 0 to t = tPHL. • At t = tPHL, NMOS will be operated in linear. tPHL

  36. VDD Vout t = 0 I VDD II III Vin t = tPHL Vout IV VDD V Vin CL Vtn VDD VDD/2 Vout Vin CL iDN LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • It is based on computing an average value for the discharge current iDN during the interval t = 0 to t = tPHL. • The average discharge current can be found as, tPHL

  37. Vout I VDD II VDD III Vin IV Vout VDD V Vin iDP Vtn VDD CL VDD/2 t = 0 Vout Vin CL LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • It is based on computing an average value for the charge current iDP during the interval t = 0 to t = tPLH. • At t = 0, PMOS will be operated in saturation. tPLH

  38. Vout t = tPLH I VDD II VDD III Vin IV Vout VDD V Vin iDP Vtn VDD CL VDD/2 Vout Vin CL LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • It is based on computing an average value for the charge current iDP during the interval t = 0 to t = tPLH. • At t = tPLH, PMOS will be operated in linear. tPLH

  39. Vout t = tPLH I VDD II VDD III Vin IV Vout VDD V Vin iDP Vtn VDD CL VDD/2 t = 0 Vout Vin CL LOGIC-CIRCUIT CHARACTERIZATION • Propagation delay • It is based on computing an average value for the charge current iDP during the interval t = 0 to t = tPLH. • The average charge current can be found as, tPLH

  40. VDD VDD Q2 Q4 Vout Vin Vout Vin Q1 Q3 LOGIC-CIRCUIT CHARACTERIZATION • Example • Consider a CMOS inverter fabricated in a 0.25-um process for which : 1. Cox = 6 fF/um-square, unCox = 115 uA/V-square, upCox = 30 uA/V-square, Vtn = -Vtp = 0.4 V, and VDD = 2.5 V. 2. The W/L ratio of QN is 0.375-um/0.25-um, and that for QP is 1.125-um/0.25-um. 3. The gate-source and gate-drain overlap capacitances are specified to be 0.3 fF/um of gate width. 4. The effective value of drain-body capacitance are Cdbn = 1 fF and Cdbp = 1 fF. 5. The writing capacitance Cw = 0.2 fF. Please find the values of tPHL, tPLH, and tp.

  41. VDD VDD VDD Vout Vin Vin CL 3 4 2 1 Cgd1 + Cgd2 Cw Cg3 + Cg4 2 1 3 4 Cdb1 + Cdb2 LOGIC-CIRCUIT CHARACTERIZATION • Example • First, determine the value of the equivalent capacitance CL at the output node. Solutions

  42. VDD VDD VDD Vout Vin Vin CL Vout I VTC Operating Modes II VDD Qn Qp I CutOff Linear III II Saturation Linear Physical Switch III Saturation Saturation IV Linear Saturation IV V Physical Switch Vin V Linear CutOff VDD Vtn LOGIC-CIRCUIT CHARACTERIZATION • Example • Consider region II & IV (the physical switch model) to find the tPHL& tPLH, respectively. Remark

  43. VDD VDD VDD VDD Vout Vin Vin Vin Vout CL CL iDN LOGIC-CIRCUIT CHARACTERIZATION • Second, consider the discharge of CL through Qn to determine tPHL(From region II to region IV). Solutions

  44. VDD VDD VDD VDD Vout Vin Vin Vin Vout CL CL iDN LOGIC-CIRCUIT CHARACTERIZATION • Second, consider the discharge of CL through Qn to determine tPHL. Solutions

  45. VDD VDD VDD VDD Vout Vin Vin Vout Vin CL iDP CL LOGIC-CIRCUIT CHARACTERIZATION • Third, consider the charge of CL through Qp to determine tPLH (From region IV to region II). Solutions

  46. VDD VDD VDD VDD Vout Vin Vin Vout Vin CL iDP CL LOGIC-CIRCUIT CHARACTERIZATION • Third, consider the charge of CL through Qp to determine tPLH. Solutions

  47. VDD VDD VDD Vout Vin Vin CL The propagation delay is, tP = (1/2)(tPHL + tPLH) = (1/2)(22.4 + 28.6) = 25.5 ps LOGIC-CIRCUIT CHARACTERIZATION • Example • Alternative thinking, Since (Wn x un) / (Wp x up) = 1.28, i.e.,iDN = 1.28 iDP, the inverter isn’t perfectly matched. Thus, Solutions

  48. where f is the frequency at which inverter is being switched. LOGIC-CIRCUIT CHARACTERIZATION • Power dissipation • Power dissipation is an important issue in digital-circuit design. • There are two types of power dissipation in a logic circuit: Static Power Dynamic power 1. The gate dissipates in the absence of switching action. 2. It results from the presence of a path in a gate circuit between the power supply and ground in one or both of its two states. The dynamic power occurs only when the gate is switched : An inverter operated from a power supply VDD, and driving a load Capacitance C, dissipates dynamic power PD.

  49. The propagation delay PD increases. LOGIC-CIRCUIT CHARACTERIZATION • Delay-Power product • High-speed performance (low tp) and low-power dissipation are both requirement in circuit design. However, these two requirements are often in conflict. • Generally, the power dissipation methods in designing a circuit are, 1. Decreasing the supply voltage or reducing the switching times 2. Decreasing the transistor size This in turn results in longer times to charge and discharge the load and parasitic capacitance. That means the channel width of a transistor is reduced, however the transistor resistor will be increased.

  50. LOGIC-CIRCUIT CHARACTERIZATION • Delay-Power product • High-speed performance (low tp) and low-power dissipation are both requirement in circuit design. However, these two requirements are often in conflict. • It follows that a figure-of-merit for comparing logic-circuit technologies (or families) is the delay-power product, defined as, • Example • A CMOS inverter in a VLSI circuit operating from a 5-V supply has (W/L)n = 10um/5um, (W/L)p = 20um/5un, Vtn =|Vtp|= 1V, unCox = 2upCox = 20 uA/V-square. (a) If the total effective load capacitance is 0.1 pF, find tPHL, tPLH, and tp. (b) Calculate the delay-power product of the CMOS inverter when it is operating at a switching rate of 50 MHz. The lower the DP figure for a logic family, the more effective it is.

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