Programming & Development of Mobile & Embedded Systems

1. Programming & Development of Mobile & Embedded Systems Lin Zhong ELEC424, Fall 2010

2. Outline • Programming basics • Programming MSP430 • Programming Windows Mobile devices

3. Programming basics • How programmable systems work Non-volatile storage Processing executables Instruction fetching Execution unit • Programming is about changing the content of non-volatile storage • PC: Hard drive • Mobile Devices: Flash ROM • MSP430: Flash ROM • Many input channels can work • PC: DVD/CD drive M, USB drive, Ethernet, Wi-Fi • Mobile Devices: USB port, Bluetooth, Cellular, Wi-Fi • MSP430: Any input (even analog!!!!)

4. Programming basics (Contd.) • How executables are generated? Compile Compile High-level language • C/C++/C#/Java • Matlab/Labview • Perl Intermediate format • Assembly • Java byte code Machine code 101010100 Machine code 101010100 Link Machine code 101010100 Machine code 101010100 • Compile & link can be done at run-time • Java & C#: second stage compilation • Perl/BASIC (interpretive languages)

5. Cross platform development • Cross compile & Cross link • Produce the machine code for a foreign platform • PCMobiledevices • X86 processorsARM processors • PCOrbit sensors • X86 processorsMSP430 • Cross development tool chains • Linux GNU ARM tool chains • Integrated development environment (IDE) • Microsoft Visual Studio • IAR Embedded Workbench

6. IDE concepts • Projects • Organized source files • Properties of target platform • Run-time debug • Debug/release modes • Emulators • Development without a physical device

7. Programming MSP430 USB cable JTAG JTAG

8. IAR Embedded Workbench • C and C++ • Software emulator • Free evaluation version

9. IAR Embedded Workbench • Project options

10. Run-time debugging

11. Getting help

12. Memory space • Unified address space • No “cache”

13. Tilt 2 vs. PC CPU Registers Cache Main memory File system cache Hard disk

14. Special function registers (SFRs) • 16 registers (R0-R15) • Program counter (PC)/R0 • Pointer to the next instruction

15. Stack pointer (SP/R1) • Store the return addresses of subroutine calls and interrupts • Stack • Last-In, First Out • PUSH • POP • Automatic allocated memory in C • You don’t need to worry about it • Take care by the compiler • Subroutine calls • Interrupt handlers

16. Status register (SR/R2) • Can be read and written Clock

17. Load-store architecture a.k.a. RISC architecture Register file MEM/Cache Execution unit Load/store

18. Interrupt-driven programming Start System idle • Clock • I/O pins • Interrupt • Periperals Initialization Interrupt Interrupt TimerA() USARTRX() Interrupt handlers

19. Initialization

20. Interrupt properties • Maskable vs. non-maskable • Nested • Priority

21. IAR EWR interrupt • Enable interrupt

22. IAR EWR interrupt • Interrupt handler is a special subroutine

23. A problem • A[0]=1; • B[0]=1; • enable interrupt there • while () { • if (A[0]!=B[0]) exit; • else continue ; • } Interrupt_handler() { A[0]=2; B[0]=2; }

24. A problem • A[0]=1; • B[0]=1; • while () { • if (A[0]!=B[0]) exit; • else continue ; • } Interrupt_handler() { A[0]=2; B[0]=2; } LD R13, (A[0]); LD R14, (B[0]) ; CMP R13, R14; JEQ EXIT

25. Critical section • A[0]=1; • B[0]=1; • while () { • if (A[0]!=B[0]) exit; • else continue ; • } Interrupt_handler() { A[0]=2; B[0]=2; } LD R13, (A[0]); LD R14, (B[0]) ; CMP R13, R14; JEQ EXIT; ……. Section of code that access a shared resource that must not be concurrently accessed by more than one thread of execution

26. Atomic operation • A set of operations that appears to be one to the system • System state change due to the operations invisible until all the operations are successful • If any of the operations fails, the entire set fails; and no change to the system state • Examples • An assembly instruction • Interrupt-disabled

27. When do we need an OS?