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Lab 5 – More State Machines. Multiple processes

Lab 5 – More State Machines. Multiple processes. Lab 5 - Mealy Outputs. Ref: Chapter 10, RTL Hardware Design Using VHDL. State diagram. Mealy Outputs. Revised state diagram (sm2). / Y=1. Y=1. / Y=0. / Y=0. ASM Chart.

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Lab 5 – More State Machines. Multiple processes

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  1. Lab 5 – More State Machines. Multiple processes

  2. Lab 5 - Mealy Outputs Ref: Chapter 10, RTL Hardware Design Using VHDL • State diagram

  3. Mealy Outputs Revised state diagram (sm2) / Y=1 Y=1 / Y=0 / Y=0

  4. ASM Chart An algorithm state machine (ASM), is an alternative method for representing an FSM. Although an ASM chart contains the same amount of information as a state diagram, it is more descriptive. It is usually used to specify complex sequence of events and actions needed to implement a control path. An ASM is composed of a network of ASM blocks.

  5. ASM Block

  6. ASM Block To reduce clutter, sometimes only the signals that are activated (asserted) are shown in the ASM. Example 1:

  7. ASM Block Example 2:

  8. ASM – More examples Example 3:

  9. ASM – More examples A counter from 0 to 8; ASM representation:

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