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Computer architecture

Computer architecture. Lecture 7: Control unit. Microoperations Piotr Bilski. Tasks of the Control Unit:. Processor’s state monitoring Control of the processor’s work Microoperations scheduling. Instruction cycle. Instruction cycle. Instruction cycle. Fetching. Indirect addressing.

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Computer architecture

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  1. Computer architecture Lecture 7: Control unit. Microoperations Piotr Bilski

  2. Tasks of the Control Unit: • Processor’s state monitoring • Control of the processor’s work • Microoperations scheduling Instruction cycle Instruction cycle Instruction cycle Fetching Indirect addressing Interrupt Execution μOP μOP μOP

  3. Microoperations • Elementarny steps in the instruction cycle • Every step is basic and its result is small • Every microoperation takes one time unit • They exist in all phases of the instruction cycle: fetching, indirect addressing, executing, interrupt

  4. Instruction Fetching Cycle Data bus Address bus Control bus Processor t1: MAR  (PC) t2: MBR  M(MAR) PC MAR Memory CU IR MBR PC  (PC) + 1 t3: IR  (MBR)

  5. Indirect Addressing Cycle Data bus Address bus Control bus Processor t1: MAR  (IR(Address)) t2: MBR  M(MAR) t3: IR(Address)  (MBR(Address)) MAR Memory CU MBR

  6. Interrupt Cycle Data bus Address bus Control bus Processor t1: MBR  (PC) t2: MAR  Address PC MAR Memory CU MBR PC  IHP address t3: M(MAR)  (MBR)

  7. Execution Cycle • The most complicated because of the branches • Example: BSA X t1:MAR  (IR(Address)) MBR  (PC) t2: PC  (IR(Address)) M()  (MBR) t3: PC  (PC) + 1

  8. Register Instruction Cycle Code (ICC) • Register storing instruction cycle code of the processor’s state, for example: • 00 – fetching • 01 – indirect addressing • 10 – execution • 11 – interrupt

  9. Model of the Control Unit Control signals inside the processor Instruction register Status flags Control Unit clock Control bus

  10. Control Signal Types • Activating functions of the ALU • Activating data path • Related to the system bus • Controlling signal types is performed by opening gates between the registers and the memory • Knowledge about the ICC status is required

  11. Internal Organization of the Processor t1: MAR  (IR(Addr)) t2: MBR  M(MAR) t3: Y  (MBR) t4: Z  (AC) + (Y) t5: AC  (Z) CU IR PC MAR Y Address lines MBR ALU Data lines Z AC Internal bus

  12. Intel 8085 Processor (1977) • Compliant with 8080 processor • Powered by +5V voltage • Structure: CU, PC, A, RA, ALU, RF, RR • Program Counter – 16 bits, address register – 16 bits, instruction register – 8 bits • External stack in RAM • ALU – processing max 2 arguments

  13. 8085 Processor Scheme

  14. Examples of the External Signals (Intel 8085) • Address and data signals • Adresses/data (A0-A7,A8-A15) • Serial input/output data (SID, SOD) • Control and clock signals • CLK, X1, X2 • Address Latch Enabled (ALE) • IO/M • Read/write control (RD, WR) • Signals initiated by memory and input/output • Interrupt signals • Processor initialization (RESET) • Power

  15. Implementations of the Control Unit Microprogram implementation • Faster (logical circuits) • Complicated • Expensive • Realization: combinatorial circuit • Used in the RISC machines Circuit implementation • Slower • Flexible • Cheap • Realization: microprogram • Used in the CISC machines

  16. Circuit Implementation Instruction register Status flags clock Control unit Clock generator Control signals

  17. Decoder 2 to 4 A B S0 S1 S2 S3 A B S0 S1 S2 S3 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

  18. Microprogram Implementation of the Control Unit • Microprogram determines the logic of the control unit work regime • Microprogram consists of the microoperations stored in the control memory • This technique was used for the first time in the System/360 (IBM) computer

  19. Horizontal and Vertical Microoperations Branch condition Control signals of the system bus Internal signals controlling the processor Microoperation address Microoperation address Function codes Branch conditions Codes instead of the control lines – decoders required

  20. Control Memory Organization Fetch cycle subroutine Indirect addressing cycle subroutine Interrupt cycle subroutine Execution cycle subroutine

  21. Control address register Logical scheduling circuits Decoder Decoder Control buffer register Microprogram Control Unit Instruction register ALU status flags Clock Control memory Read Control signals inside CPU Control signals of the system bus

  22. Microoperations Sequencing • Instruction size and time of the address generation • The next microoperation address is: • Inside instruction register (at the beginning of the instruction cycle) • In the branch (the most common) • Next in the sequence

  23. Sequencing Methods • Two address fields • One address field • Changing format

  24. Branch logi-cal circuits Sequencing with Two Address Fields CAR Address decoder Control memory Status flags Con-trol CBR Address2 Address1 Multiplexer IR

  25. CAR Address decoder Control memory Branch logi-cal circuits One Address Field Sequencing Status flags +1 CBR Address Control Multiplexer IR

  26. CAR Address decoder Control memory Branch logi-cal circuits Changing Format Sequencing Status flags +1 CBR Branch field Whole field Address field Gating logical circuits IR Multiplexer

  27. Address Generation Evident • Two fields • Conditional branch • Uncoditional branch Non-evident • Projection • Addition • Residual control

  28. Non-Evident Projection: Addition Address register Constant part of the address Bits set to determine the address of the next microoperation

  29. Sequencing Microoperations in LSI-11 • 22-bit microoperation • About 4 KB of the control memory • Methods of the next address generation: • Next in line • Projection of the operation code • Standard subroutine • Interrupt testing • Branch

  30. Microoperations Execution • Microoperation cycle consists of the fetching and execution phase • Execution causes putting on the internal and system bus control signals and determining the next instruction address • Combination of the control bits related to the microoperation is encoded

  31. Decoders Decoders Decoders Direct Microoperation Encoding Field Field Field Control signals

  32. Decoders Decoders Decoders Decoders Indirect Microoperation Encoding Field Field Field Control signals

  33. 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 Examples of the Vertical Instructions MBR  Register Register  MBR MAR  Register Read from memory Write to memory AC  AC + Register

  34. Examples of the Horizontal Instructions 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 • Register transfer • Memory operation • Sequencing operation • ALU operation • Register selection • Constant 1 2 3 4 5 6

  35. LSI-11 Microoperation Format • Instruction breadth: 22 bits • Microoperation list is complementary to the machine instruction list 4 1 1 16 Special functions Encoded microoperations Return register loading Translation

  36. IBM 3033 Microoperation Format • Control memory – 4 KB words • Instructions from the interval 0000-07FF are 108-bit long • Instructions from the interval 0800-0FFF are 126-bit • Instructions are horizontal with coding

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