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ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs

Learn about real time interrupts in microcomputer systems, including their application, usage, and differences from timer overflow interrupts.

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ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs

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  1. ECE 3430 – Introduction to Microcomputer SystemsUniversity of Colorado at Colorado Springs Lecture #15 Agenda Today: • Real Time Interrupts • BRSET, BRCLR, BSET, BCLR instructions (I do not recommend the use of these in this class) ECE 3430 – Intro to Microcomputer Systems Fall 2009

  2. Real Time Interrupts Real Time Interrupts (RTI)- Used to generate periodic interrupts at a pre-programmed interval. - Very similar in concept to the timer overflow interrupt we already discussed—but logically disjoint! - The period for the interrupts is programmable using the PACTL register ($0026)RTR1RTR0E/213 Interrupt Period (Eclk = 2MHz) 0 0 1 4.10 ms 0 1 2 8.19 ms 1 0 4 16.38 ms 1 1 8 32.77 ms - The pre-scalar values applied to the free-running 16-bit counter (TCNT) have no effect on the real-time interrupt rate. Only the bits above specify the interrupt rate relative to E-clock frequency. - Real Time Interrupts are maskable interrupts. - Global Enable: I-bit in CCR - Local Enable: RTII bit in TMSK2 register ($0024) RTII = 0 = disabled (RESET State) RTII = 1 = enabled ECE 3430 – Intro to Microcomputer Systems Fall 2009

  3. Real Time Interrupts Real Time Interrupt (RTI) - When an interrupt occurs, it will set the RTIF flag (Real Time Interrupt Flag) in the TFLG2 control register ($0025). RTIF = 0 = no interrupt yet RTIF = 1 = an interrupt has occurred—but hasn’t been serviced (pending) - Write a ‘1’ to the RTIF bit to clear the flag. You do this in the interrupt service routine (ISR). Remember, this is a flag register (writing 1 clears bits, writing zero has no effect). So what’s the difference between real time interrupts and timer overflow interrupt? - Timer overflow has longer periods (32.77 ms, 131.1 ms, 262.1 ms, 524.3 ms). - Real time interrupts have shorter periods (4.10 ms, 8.19 ms, 16.38 ms, 32.77 ms). - Just another way to generate periodic interrupts. Disjoint from timer overflow interrupt. - Real time interrupts can interrupt faster. ECE 3430 – Intro to Microcomputer Systems Fall 2009

  4. Real Time Interrupts Real Time Interrupt Applications Multi-Tasking - The shorter period times are suitable for switching between multiple tasks. - Used by operating systems to establish a time quantum (the least amount of time a given thread is allowed to use the CPU). Periodic Processing - Use your imagination. - Updating a clock with fine resolution. ECE 3430 – Intro to Microcomputer Systems Fall 2009

  5. Other Branch Instructions Two branch instructions we didn’t discuss: BRSET: Syntax: BRSET $24 %00001100 LABEL Operation: (NOT M($0024)) AND %00001100 ?= 0 Description: If bits 2 and 3 in memory location $0024 are both logic 1, then go to line “LABEL”. BRCLR: Syntax: BRCLR $24 %00001100 LABEL Operation: M($0024) AND %00001100 ?= 0 Description: If bits 2 and 3 in memory location $0024 are both logic 0, then go to line “LABEL”. These instructions perform the equivalent of a combination of instructions: BRSET: Load M($0024), invert loaded value, load mask, AND values together, throw away result, branch to LABEL if Z bit in CCR is one (result of AND is zero). BRCLR: Load M($0024), load mask, AND values together, throw away result, branch to LABEL if Z bit in CCR is one (result of AND is zero). I DO NOT RECOMMEND THE USE OF THESE IN THE LAB! ECE 3430 – Intro to Microcomputer Systems Fall 2009

  6. Bit Setting and Clearing (Alternate Instructions) The HC11 provides bit set and bit clear instructions to expedite the setting or clearing of bits in control registers: BSET: Syntax: BSET $24 %10010000 Operation: M($0024) M($0024) OR %10010000 Description: Sets bits 7 and 4 without changing the other bits in memory location $0024. BCLR: Syntax: BCLR $24 %10010000 Operation: M($0024) M($0024) AND (NOT %10010000) Description: Clears bits 7 and 4 without changing the other bits in memory location $0024. These instructions perform the equivalent of a combination of instructions: BSET: Load $0024, load mask, OR together, store back to $0024. BCLR: Load $0024, load mask, invert mask, AND together, store back to $0024. I DO NOT RECOMMEND THE USE OF THESE IN THE LAB! THERE ARE TIMES WHEN THE USE OF THESE INSTRUCTIONS CAN GET YOU INTO TROUBLE! USE EXPLICIT LOGIC MASKS AND LOAD AND STORE OPERATIONS! ECE 3430 – Intro to Microcomputer Systems Fall 2009

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