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Power/Ground Pin Parasitic for SSN Simulations - A Literature Review-

Power/Ground Pin Parasitic for SSN Simulations - A Literature Review-. Ambrish Varma akvarma@ncsu.edu. August 2005. Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices. R. Senthinathan and J. L. Prince

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Power/Ground Pin Parasitic for SSN Simulations - A Literature Review-

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  1. Power/Ground Pin Parasiticfor SSN Simulations -A Literature Review- Ambrish Varma akvarma@ncsu.edu August 2005

  2. Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices R. Senthinathan and J. L. Prince 1724 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 11, NOVEMBER 1991 http://ieeexplore.ieee.org/iel1/4/3123/00098995.pdf?arnumber=98995

  3. Electrical Packaging Requirements for Low-Voltage ICs-3.3 V High-Performance CMOS Devices as a Case Study Ramesh Senthinathan,Arun Mehra, Mali Mahalingam, Yutaka Doi, and Hector Astrain IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART B, VOL. 17, NO. 4, NOVEMBER 1994 http://ieeexplore.ieee.org/iel4/96/7951/00338714.pdf?arnumber=338714

  4. Accurate Simultaneous Switching Noise Estimation Including Velocity- Saturation Effects Srinivasa R. Vemuru, IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART B, VOL. 19, NO. 2, MAY 1996 http://ieeexplore.ieee.org/iel4/96/10657/00496038.pdf?arnumber=496038

  5. Estimation of Ground Bounce Effects on CMOS Circuits Adnan Kabbani and Asim J. Al-Khalili IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGY, VOL. 22, NO. 2, JUNE 1999 http://ieeexplore.ieee.org/iel5/6144/16812/00774752.pdf?tp=&arnumber=774752&isnumber=16812

  6. Simultaneous Switching Noise (SSN) Modeling Bernhard Unger 1/31/00 EIA IBIS Summit http://www.industry.siemens.de/itps/eda/download/ibis_summit200.pdf

  7. Analysis and Optimization of Ground Bounce in Digital CMOS Circuits Payam Heydari and Massoud Pedram IEEE International Conference on Computer Design (ICCD), Austin, Texas, Sept. 2000. http://newport.eecs.uci.edu/~payam/ICCD2000.pdf

  8. Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits Kevin T. Tang and Eby G. Friedman Proceedings of the International Conference on Modeling and Simulation of Microsystems, 2000 http://www.nsti.org/publ/MSM2000/T31.03.pdf

  9. Noise Generation and Coupling Mechanisms in Deep-Submicron ICs Xavier Aragonès, Jose Luis González, Francesc Moll, and Antonio Rubio Universitat Politècnica de Catalunya IEEE Design & Test of Computers. September–October 2002 http://ieeexplore.ieee.org/iel5/54/22200/01033789.pdf?arnumber=1033789

  10. Simultaneous Switching Noise in On-Chip CMOS Power Distribution Networks Kevin T. Tang and Eby G. Friedman, Fellow, IEEE IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST 2002 http://ieeexplore.ieee.org/iel5/92/26443/01177355.pdf?tp=&arnumber=1177355&isnumber=26443

  11. Analyzing Internal-Switching Induced Simultaneous Switching Noise Li Yang, J. S. Yuan Proceedings of the Fourth International Symposium on Quality Electronic Design (ISQED’03) http://ieeexplore.ieee.org/iel5/8500/26872/01194768.pdf?tp=&arnumber=1194768&isnumber=26872

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