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Operating Systems

Operating Systems. Certificate Program in Software Development CSE-TC and CSIM, AIT September -- November, 2003. Objective to give a (selective) overview of computer system architectures. 2. Computer-System Structures (Ch. 2, S&G). Contents. 1. A Modern Computer System 2. Interrupts

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Operating Systems

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  1. Operating Systems Certificate Program in Software DevelopmentCSE-TC and CSIM, AITSeptember -- November, 2003 • Objective • to give a (selective) overview of computer system architectures 2. Computer-System Structures(Ch. 2, S&G)

  2. Contents 1. A Modern Computer System 2. Interrupts 3. I/O 4. Caching 5. Protection

  3. Line Printer 1. A Modern Computer System Fig 2.1, p.24 CPU diskcontroller printercontroller tape-drivecontroller system bus memorycontroller I/O controller I/O controller memory continued

  4. CPU and device controllers (drivers) can execute concurrently. • Access to shared memory must be controlled. • A hard-wired bootstrap program loads and starts the OS kernel.

  5. 2. Interrupts • Modern OSes are driven by interrupts (traps) sent when events occur in hardware or software. • Types of events: • completion of I/O, division by 0, system calls, etc. continued

  6. An interrupt causes the OS to stop its current task, and switch execution to an interrupt-processing routine. • At the end of the routine, the old task is resumed • the old task’s details must be stored during the interrupt processing continued

  7. The addresses of the interrupt routines are stored in a fixed segment of memory (an interrupt vector). • The OS selects a routine from the interrupt vector based on the ‘type’ of the interrupt it received. continued

  8. Features of interrupts: • disabling of other interrupts during interrupt processing • prioritisation

  9. System Calls Fig 2.9, p.44 • System calls are implemented using interrupts. resident monitor case n:read: 2 1 perform I/O trap tomonitor :system call n: 3 return user program

  10. 3. I/O • Synchronous I/O • the user process waits during I/O processing • Asynchronous I/O • control returns to the user without waiting for the I/O to complete

  11. I/O Forms Fig. 2.3, p.27 Synchronous Asynchronous requesting process requesting process user user device driver device driver interrupt handler interrupt handler kernel kernel hardware data transfer hardware data transfer time time

  12. 3.1. Synchronous I/O • Waiting is done either with: • a special wait instruction • a busy-wait loop, such as: loop: jmp loop • A busy-wait generates instruction fetches, and so may lead to contention with the I/O. • Only one I/O process involved.

  13. 3.2. Asynchronous I/O • Big advantage: the CPU is not affected while slow I/O is carried out. • Many I/O requests can be in action at once • the implementation requires an I/O device status table

  14. I/O Device Status Table Fig 2.4, p.28 dev: card reader 1status: idle PID: 3445addr: 34556length: 1345 dev: line printer 3status: busy dev: disk unit 1status: idle dev: disk unit 2status: idle file: xxxop: readaddr: 23456length: 2000 file: yyyop: writeaddr: 6543length: 500 dev: disk unit 3status: busy ::

  15. 3.3. Direct Memory Access (DMA) • Device controllers transfer data blocks to/from memory directly, bypassing the CPU • only one interrupt generated per block • much faster than interrupt driven character transfer

  16. 3.4. Memory Mapped I/O • I/O device registers is mapped to memory so that reads/writes to those memory addresses go straight to the device • used for fast and frequently used device • e.g. video controller, serial port

  17. 4. Caching • The cache is fast memory between the CPU and main memory • the CPU looks in the cache first for data • new data taken from main memory is also placed in the cache for quick access next time • Instruction caching • Cache management • can affect performance drastically

  18. Cache Coherency • Must ensure that the data in the cache is always the same as its original version in main memory. • Complicated by multiprocessor and distributed environments • several caches, replicated memory

  19. 5. Protection • 5.1. Dual-mode Operation • 5.2. Memory Protection • 5.3. CPU Protection

  20. 5.1. Dual-mode Operation • User mode • Monitor mode • supervisor mode, root, superuser, system mode, priveleged mode • Implemented in hardware • OS always runs in monitor mode

  21. 5.2. Memory Protection • The interrupt vector must be protected from modification by users. • The interrupt processing routines must be similarily protected.

  22. Partitioning Memory Fig 2.7, p.40 0 monitor 256000 job 1 300040 300040 job 2 base register 420940 job3 120900 limit register 880000 job4 1024000

  23. Fig 2.8, p.41 • Only addresses within the job’s memory space are accessible. memory base base + limit address yes yes CPU >= < no no trap to OS monitor -- addressing error

  24. 5.3. CPU Protection • Each process is interrupted after a fixed time • this breaks infinite loops in poor code which would otherwise hog the CPU • allows the OS to time-slice users by context switching

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