A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in CT SDM

1. A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in CT SDM Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins Analog and Mixed Signal VLSI Laboratory University of Macau Presenter:Yang Jiang

2. Contents • Introduction to Clock-Jitter in CT SDMs • Existed Solutions • Fixed-Pulse Shape Feedback Technique • CT SDM Design Example • Simulation Results • Conclusion

3. Introduction Clock-Jitter in CT SDM Clock-jitter effect is worse in RZ case ! Pulse Width (PW) Random Variation White Noise in every clock cycle

4. Existed Solutions Shaped-Feedback Waveform (RZ) Principle:Minimize the FB pulse at the end of the feedback phase to reduce the PW variation effect. [Traditional] [SCR] [SCSR] PW variations×× Peak current √√ PW variations√√ Peak current ×× Implementation √ PW variations√ Peak current √ Implementation ×

5. Fixed-Pulse Shape Feedback Fixed-Pulse Shape (RZ) Principle:Fix the FB PW independent of the jittered clock. [Traditional] Proposed Technique Benefit: Generate precise FB pulse with appropriate peak current. PW variations×× Peak current √√ PW variations√√ Peak current √ Implementation √√

6. Fixed-Pulse Shape Feedback Proposed RCDD Structure Idea:Generate a fixed time interval based on RC discharge process. ClockIndependent RC Discharge Detection (RCDD) Circuit

7. Fixed-Pulse Shape Feedback RC Variation Effect FB RC Variation Insensitive

8. Fixed-Pulse Shape Feedback RC Variation Effect Td Tr FB PW Leave enough margin for Tr .

9. Fixed-Pulse Shape Feedback Clock-Jitter Insensitivity Clock-jitter Immune ! ΔTr do not affect FB PS.

10. CT SDM Design Design Specifications ≥ 10-bit Implement Proposed Tech. / ELD Tolerant Stability Linearity WCDMA

11. CT SDM Design Circuit Implementation - RC Integrators - SR Feedback - Dynamic Comparator - VDD = 1 V - VCM = 500 mV

12. CT SDM Design Feedback DAC RCDD Circuit Polarity Judgment Switched-Resistors

13. Simulation Results Simulated PSD Test input: -2dBFS @ 100kHz 76dB 56dB 81dB Traditional 0 jitter RCDD 1% jitter Traditional 1% jitter 1% clock-jitter effect No clock-jitter effect SNDR = 63dB, SFDR = 76dB SNDR = 43dB, SFDR = 56dB SNDR = 67.5dB, SFDR = 81dB

14. Simulation Results Clock-Jitter Sensitivity 62dB (10-bit) 30dB 0.08% 3% Test input: -2dBFS @ 100kHz

15. Simulation Results Performances Summary CT SDM Performances

16. Conclusion • A Feedback technique with reduced clock-Jitter sensitivity is proposed. • Using RC discharge detection (RCDD) technique to fix FB pulse-shape. • Accurate FB can be achieved (RC-variation tolerant). • Full transistor-level CT SDM was designed. • Simulation result verified the effectiveness of the proposed technique.

17. Reference • [SCSR] M. Anderson and L. Sundstrom, “Design and measurement of a CT ΣΔ ADC with switched-capacitor switched-resister feedback”, IEEE J. Solid-State Circuit, vol. 44, no. 2, pp. 473-483, February, 2009. • [SCR] M. Ortmanns, F. Gerfers, and Y. Manoli, “A continuous-time ΣΔ modulator with reduced sensitivity to clock jitter through SCR feedback,” IEEE Trans. Circuits System I, Regular Paper, vol. 52, no. 5, pp. 875–884, May 2005.

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