CERN ETD Meeting Summary - TDR Writing and Main Points Discussed

1. ETD/Online General SessionSummary of CERN meeting – TDR writingD. Breton Frascati Meeting 12/2011

2. Main items of discussion at CERN Wednesday Thursday Synchronous, Pipelined, Fixed-Latency

3. Main points out of CERN ETD meeting • We had a 2-day ETD meeting last month at CERN • The goal of the meeting was to thouroughlydiscuss what will be written in the TDR. • We had plenty of time to go through all the subsystems and discuss all the necessary points. • Nothing was left apart. • We especially focussed on: • the feeding of the derandomizer and readout link from the latency buffer • the number of readout links and their occupancy • the tolerance to radiation of the design • We made a big progress in the common understanding of the system. • We defined almost all the baselines, options and the potential upgrades to describe in the TDR. • We realized that the distance between triggers is not necessarily a source of deadtime if it remains reasonable (~50ns) => this has to be further studied

4. TDR : where are we ? (1) • FCTS : mostly defined at the architecture level. The remaining question is about the physical implementation (type of crate, size of the boards) • µTCA in its 6U HEP implementation (xTCA) seems to be a good candidate • trigger group is having a look at it • ECS : mostly defined (based on LHCb’s equivalent system => SPECS bus) • => work is currently ongoing to test the Ethernet implementation of the SPECS master within FPGAs • Trigger : no major concern for trigger processors. Main concern is the time precision which directly impacts the dead-time and dataflow. • => but discussions at CERN tended to show that if the trigger time windows are properly scaled, time precision (if kept raisonable) doesn’t directly impact the dead-time because data of two close physics events resides within the same DAQ event

5. TDR : where are we ? (2) • Clock and Control Links : • 92LV18 SERDES ok for dose but showed potential problems of loss of lock in case of SEUs. • FPGAs have been tested in radiation but currently available families are not tolerant enough for our purpose. • However, next versions may behave a better way • => baseline remains to use SERDES with embedded clock (either specific chipset or FPGA) for simplicity reasons • => safety backup is to have a separated clock distribution • => effect of potential loss of commands has to be farther studied • Readout links : still no baseline. No SuperB candidate yet. Not mandatory to have a fixed latency, neither a synchronous clock. • New chipsets have to be validated for radiation. • GOL could be used as a backup (baseline ? ). • Link and mezzanines will be upgradable to permit increasing the data rate.

6. TDR : where are we ? (3) • Use of mezzanines for links out of detector : no strong decision made here. There are still different positions among different groups and the conveners. Main problem is the extra space needed to implement the mezzanines. • to be farther discussed • redaction of TDR may leave this choice « open » at this time (two options) • Common Front-End Electronics : • clearly defined/simulated for ADC-based subsystems. • CERN meeting permitted to also present a solution for implementing the latency buffer in the case of random hit-based subsystems (like PID) • => Nice solution because it makes the derandomizing operation standard for all cases => common FEE design (except for SVT) • ROM : two solutions under study (boards/PCs). • One has to be defined as baseline and the other as backup/upgrade • To me, the hardware-based one seems to be leading the game for simplicity and manpower availability reasons …

7. ASIC ASIC ADC latency latency Reminder of the CFEE proposal FPGA Go_back_in_time start_flag, go_back, Mn Fifo “M” 16 Bits !empty COMB Trigger Latency W’ wr_en Mn Mn FSM end wr_en delayed Δt W enable FSM registers Mn Counter ECS L W’ W rd empty 112 Mhz Wr_en 256 Bits Digital Data 17x16 bits Latency Pipeline Data_in Data_out M U X 16 bits 1.8 GBits/s Tx L + W’ Event Buffer to ROM 112 Mhz rd clk rd Analog Data clk Wr_en Extra latency 17x16 bits rd clk Data_out M U X 16 bits Data_in Hits 1.8 GBits/s Tx Event Buffer to ROM 112 Mhz

8. How to resynchronize “random” hits from TDC: example of PID FPGA Time counter Synchronous counters SCATS chip Comp Ch0 Latency Pipeline Ch0 TDC FIFO Ch0 DEM U X M U X Dual port RAM TDC FIFO Ch15 Comp Ch15 Latency Pipeline Ch15 clk clk clk clk clk Dual port RAM Only difference with continuous (ADC-based) implementation: only time slots with valid hits (red points) will be transfered to the derandomizer.

9. Power supplies & general TDR writing • Power supplies : at the end of the CERN meeting, our new collaborator GianluigiPessina from Milano proposed to take care of these elements for the whole experiment. • This is great news ! • We prepared together a dedicated questionnaire • Answers this questionnaire (sent last week) should be presented and discussed during this session • The goal is to standardize the supply systems as much as possible (LV & HV) • TDR writing : • Steffen started preparing the new organization of the chapters (Intro/overview chapter in the front with intro to the detector, 3 chapters ELEX, TRG, DAQ/Online) • At the end of the CERN meeting, all subsystems had everything in hand to write their drafts for electronics. They are supposed to discuss and present them tomorrow => we are waiting for their contributions • Concerning the ETD specific elements, work is ongoing. No major change since white paper. Updates are as presented in the former slides.

10. ETD organization for TDR (to be refined) • Conveners : D.Breton (LAL Orsay), U.Marconi (INFN Bologna), S.Luitz (SLAC) • FCTS : LAL Orsay (D.Charlet) • ECS : LAL Orsay (D.Charlet) • Trigger : INFN Roma-3 (P.Branchini) • Clock and Control Links : University of Napoli (A. Aloisio) • Readout links : University of Napoli (A. Aloisio) • Common Front-End Electronics: LAL Orsay (J.Maalmi) • ROM : INFN Bologna (U. Marconi) • Power supplies : INFN Milano (GianluigiPessina) • DAQ/Online : SLAC (S.Luitz) • TDR editor : SLAC (S.Luitz) • Subdetector contacts : • SVT : INFN Pisa (M.Villa) • DCH : LNF (G.Felicci) • PID : LAL Orsay (C.Beigbeder => Barrel, D.Breton => Forward) • EMC : INFN Roma-1 (V.Bocci => Barrel & Forward), Backward ? • IFR : INFN Ferrara (A. Cotta)