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SuReal – Sicherheitsgarantien unter Realzeitanforderungen

SuReal – Sicherheitsgarantien unter Realzeitanforderungen. Jonas Rox Braunschweig, 22.04.2008. Gliederung. Überblick: Das SuReal Projekt SuReal am IDA. Projektvision. Einsatz spezialiserter Tools in den einzelnen Phasen Integration in einheitlichen Entwicklungsprozess

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SuReal – Sicherheitsgarantien unter Realzeitanforderungen

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  1. SuReal – Sicherheitsgarantien unter Realzeitanforderungen Jonas Rox Braunschweig, 22.04.2008

  2. Gliederung • Überblick: Das SuReal Projekt • SuReal am IDA

  3. Projektvision • Einsatz spezialiserter Tools in den einzelnen Phasen • Integration in einheitlichen Entwicklungsprozess • Integrierte Toolchain

  4. Der SuReal Entwicklungsprozess (Okt.2007) DFKI ScopeSET Symtavision TU Braunschweig TU Dresden aicas AbsInt TU München

  5. Integration der spezialisierten Tools • Eclipse als zentrale Toolplattform für SuReal • AMEOS und UPPAAL über Plugin mit Eclipse verbunden • Analyse Tools selbst gar nicht sichtbar, liefern Ergebnisse auf Knopfdruck

  6. Verbindungen IDA - Projektpartner Rückannotation von Analyseergebnissen AP2 - 5 AP6 aicas Scopeset DFKI TUD Realzeitanforderungen IDA AbsInt TUM Kernlaufzeiten Symtavision AP7,8 Analyseergebnisse

  7. SuReal am IDA • Verfeinerung eingesetzter Modelle und Analyseverfahren zur Berücksichtigung von RTE und com-Layer Hierarchische Ereignismodelle zur Modellierung hierarchischer Ereignisströme • Optimierte Verteilung von Softwarefunktionen auf Komponenten einer verteilten HW-Architektur Mapping Exploration

  8. Modeling Event Stream Hierarchies with Hierarchical Event Models

  9. Compositional approach Tasks are coupled by event sequences Composition by means of event stream propagation Apply local scheduling techniques at resource level Determine the behavior of the output stream Propagate to the next component T3 C1 T1 T4 C2 T2 CPU Bus CPU system input system output

  10. The SymTA/S model Time number of events 5 4 3 2 1 2 3 4 5 number of events time interval C1:[4,7] T3 C1 T1 T4 C2 T2 CPU Bus CPU system input system output T4:[3,5]

  11. The challenge • Consider the presence of communication layers signal values signal values frame activations frame arrivals T1 T3 C Buf Buf T2 T4 COM COM ECU Bus ECU system output system input signal values signal values

  12. Using the existing model T1 T3 C Buf Buf T2 T4 COM COM ECU Bus ECU ? ? No timing information about the individual event streams available!

  13. T1 T3 C Buf Buf T2 T4 COM COM ECU Bus ECU Using the hierarchical model

  14. What we have at this point: One outer event stream modeling the frame activations One inner event stream for each sending task: Events represent frames that contain a new signal from the corresponding task Packing the signals T1 T3 C Buf Buf T2 T4 COM COM ECU Bus ECU Total frame activations T1 T2

  15. What we have at this point: One outer event stream modeling the frame arrivals One inner event stream for each sending task: Events represent frames that contain a new signal from the corresponding task Unpacking the signals T1 T3 C Buf Buf T2 T4 COM COM ECU Bus ECU Total frame arrivals T1 T2 The inner event streams directly give us the timing of the specific signal arrivals

  16. Next steps • Make use of better propagation mechanism • Improved output jitter calculation [Rafik07] • Schliecker’schen busy times

  17. Prototypische Implementierung der Mapping Exploration

  18. Mapping Exploration - Eingabedaten Beschreibung der Applikation in Form eines Applikationsgraphen Beschreibung der Hardware-Architektur Beschreibung der benötigten Ausführungszeiten einzelner Tasks Timing Constraints (Optional) Z.B. :[Sensor1 -> Actor1] 350ms T5 T1 T2 T7 T6 T0 Actor 1 Sensor 1 T3 T4 Sensor 1 Actor 1 ECU3 ECU1 ECU2 BUS 1

  19. Mapping Exploration - Ablauf Mapping Exploration 1.4. Annotate Fitness Values Mapping Mapping Execution Demands Timing Constraints SymTA Systems Mapping Mapping 1.2 1.3 Mapping 1.1 Synthesis Evaluation Mapping Alternatives Mapping Mapping Mapping Application Description Offspring Mappings Repair Function Validity Check 2.1 3.2 3.1 Architecture Description Evolutionary Optimizer 2.2

  20. Mapping Exploration - Implementierung

  21. Thank you!

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