Experiment 8 Introduction

1. Experiment 8Introduction

2. Experiment 8 FPGA Joysticks BRAM & Post Processing (VHDL) Camera (Handle-C) VGA output (Handle-C) Camera API: RC10CameraRun (CameraMode, ClockRate) RC10CameraRead<Mode> (&X, &Y, &Pixel) VGA API: RC10VideoOutRun (VIDMODE, ClockRate) RC10VideoOutGetX() RC10VideoOutGetY() RC10VideoOutWrite(color)

3. Mixing Handel-C with VHDL

4. VHDL in Handel-C (1) ENTITY parmult IS port ( clk: IN std_logic; a: IN std_logic_VECTOR(7 downto 0); b: IN std_logic_VECTOR(7 downto 0); q: OUT std_logic_VECTOR(15 downto 0)); END parmult; interface parmult (unsigned 16 q) parmult_instance (unsigned 1 clk, unsigned 8 a, unsigned 2 b) with {busformat = "B(I)"};

5. VHDL in Handel-C (2) unsigned 8 x1, x2; unsigned resultX; interface parmult (unsigned 16 q) parmult_instance1 (unsigned 1 clk = __clock, unsigned 8 a = x1, unsigned 8 b = x2 ) with {busformat = "B(I)"};

6. VHDL in Handel-C (3) while (1) { par { x1 = some_value; x2 = some_value; resultX = parmult_instance1.q; } }

7. Handel-C in VHDL (1) component handelc_component port ( clk : in std_logic; sent_value : in unsigned (3 downto 0); return_val : out unsigned (3 downto 0); ); end component;

8. Handel-C in VHDL (2) unsigned 4 x; interface port_in (unsigned 1 clk with {clockport=1}) ClockPort (); interface port_in (unsigned 4 sent_value) InPort (); interface port_out () OutPort (unsigned 4 return_value = x); set clock = internal ClockPort.clk; void main(void) { unsigned 4 y; y = InPort.sent_value; // Read from top-level VHDL x = y; // Write to top-level VHDL }

9. Mixed Handel-C / VHDLDesign Flow

10. Handle-C Process Flow Handle-C files compile *.ngc files build *.bit files

11. Mixing VHDL and Handle-C Handle-C files VHDL Verilog files compile synthesis *.ngc files *.ngc files build *.bit files

12. VHDL to NGC file • Need to synthesize VHDL source files into NGC files. • Should not map to IO ports. Check the selection.

13. Include NGC file to Handle-C Project • Copy the NGC file to the Handle-C working folder (example: RC10 in this case)

14. Include EDF to Handle-C project • Copy EDF file to the Handle-C working folder (RC10). • Add command “NDGBUILD <file>.EDF <file>.NGD” in the Command table before EDIFMAKE_RC command.

15. Resource Reports • Look in the *.PAR file under Handle-C working folder. • Or XML file under “Reports” folder.

16. Timing Report • Open Timing Analyzer tools (from Active-HDL or Xilinx project)

17. Timing (cont) • Open design files under Handle-C working folder (NCD, PCF) • Analyze

18. Lab8 Demo • Open RC10 Project under Lab8 folder. • For reference, under Lab8 Reference folder: • VHDL source code: RBG.vhd • Example for Camera->VGA in Handle-C: DefaultCamera.hcc (PSL example) • DefaultCamera.bit is the demo.