A Unified Approach to Fast Digital Processing for Beam Dampers, Instrumentation, & Controls

1. A Unified Approach toFast Digital Processing for Beam Dampers, Instrumentation, & Controls Bill Foster July ‘02

2. What’s the Scoop? 1) Fast, High Precision Pipelined ADC’s • AD6645: 14 Bits, 105 MHz, SNR 72+ dB • AD9430: 12 Bits, 210 MHz, SNR 65+ dB 2) Fast , huge FPGA’s • e.g. Altera Stratix & Apex devices • Pre-built DSP blocks including 250 MHz digital filters • > 20 GMAC/s per chip • 10 Mbits on-chip RAM, 1 Gbit/sec/pin digital I/O • glueless LVDS interface to fast ADCs

3. Generic Hardware Concept for Accelerator Instrumentation & Control 53 MHz, TCLK, MDAT,... Cables from Tunnel INPUTS: BPM Stripline Pickup Resistive Wall Flying Wire PMT RF Fanback Kicker Monitor …etc. FAST ADC Minimal Analog Filter Monster FPGA CPU Bus VME/ VXI/ PCI/ PMC etc. 14 . . . . . . . . . FAST ADC Minimal Analog Filter OUTPUTS: Stripline Kicker RF Fanout Analog Monitor …etc. FAST DAC

4. Five Example Applications using this same basic hardware: 1) Universal Beam Position Monitors (BPMs) • Handles full variety of FNAL beam RF structure 2) Generic instrumentation readout “Scope” • ex: Flying Wire readout for arbitrary bunches 3) Recycler / Injection Damper (fixed frequency) • Bunch-by-bunch, narrow band, or both at once. • Transverse and Longitudinal 4) Beam Loading Compensation 5) Universal Beam Dampers / Beamline Tuner

5. 105 MSPS AD6645 You can (basically) buy this... • Prieto, Meyer et. al. evaluating 65MHz DDC for RR BPM upgrade • Asmanskas, Foster purchasing 105 MHz version for RR Dampers

6. Echotek ADC / DDC Board • Board similar to this originated at SLAC • Local users: Prieto, Meyer, Voy & Co. • Digital Down Conversion Chip implements specific filtering algorithm (many parameters) • Same chip used by Chase et. al. on board for e-cooling BPM with excellent results • Echotek Board Includes medium-sized FPGA & Output FIFO, (can bypass DDC chip) It is possible that we can do everything we need inside the FPGA, without DDC chip.

9. AD6645 Functional Block Diagram • Two-Stage Pipelined ADC • Internal Track & Hold • Differential Analog Inputs

11. Application #1: Universal BPM(Beam Position Monitor) • Measures position of each bunch on each pass around the ring with full-bandwidth FIR filter • (R-L)/(R+L) for each bunch measurement. • Multi-bunch averages available for lower noise • per batch, per turn, many turns, different bandwidths • Multiple users can share hardware w/o conflicts • ADC is always active, FPGA stores data many ways Same Hardware OK for Booster, MI, RR, TeV, & beamlines.

12. “Universal BPM” Hardware 53 MHz, TCLK, MDAT,... 106 MHz Split Plate Pickup #1 Minimal Analog Filter Monster FPGA(s) ADC R 14 Minimal Analog Filter CPU Bus VME/ VXI/ PCI/ PMC etc. L ADC . . . . . . Pickup #4 Minimal Analog Filter ADC T Minimal Analog Filter B ADC Analog Position Monitor Test Point (Optional) FAST DAC

13. Appropriate Digital Filtering can deal with all these Bunch RF Structures

14. “Universal BPM” Application: Signal Processing Steps Echotek Board 1) Bandwidth-Limit input signal to ~53 MHz 2) 14 Bit Digitization at 106 MHz / 212 MHz 3) FIR filter(s) to get single-bunch signal(s) 4) Sum & Difference of plate signals 5) (Difference / Sum) gives position 6) Linearization lookup table or polynomials 7) Bunch, Batch, Multiturn Averaging 8) “Scope Trace Buffers” on every signal Multiple users can be acquiring and filtering data multiple ways without conflicts Inside FPGA

15. “Universal BPM” Signal ProcessingStep #1: Bandwidth Limit Signal • Raw signal has high-frequency components which can cause signal to be missed by ADC • “Aliasing” • Bandwidth limited signal (to ~53 MHz) cannot be missed by 106 MHz ADC • Example: Gaussian Filter • Eliminate low-frequency ripple, baseline shifts, etc. with Transformer or AC coupling • Digital Filtering can provide additional rejection

16. BPM Signal Doublet • Positive signal as image charge arrives, negative as it leaves ==> Bipolar Doublet This signal is too fast - can be missed by 100 MHz ADC

17. Signal From Long Stripline If Stripline Length > Beam Pulse Length, we get two separate opposite-polarity pulses

18. If Beam Pulselength > Pickup Length • Shape is ~ the derivative of the beam current. • Pulse height is reduced: VOUT ~ 1/(FWHM)2 This type of signal sets low end of Dynamic Range

19. Gaussian Filter - Impulse Response • Many implementations, e.g. traversal filter Spreads signal +/-5ns in time so it will not be missed by ADC Reduces ADC Dynamic Range requirement, since spike does not have to be digitized

20. Gaussian Filter - Doublet Response Filtered Output Pulse Shape is insensitive to Bunch Length (for Tb < 10ns) Filtered Signal can be sampled by 100 MHz ADC Digitized Pulsehight is “A - B”

21. Gaussian Filter - Pulse Train Response Filter Output is good sine wave independent of bunch length “A - B” still gives good bunch-by-bunch measurement Can digitally average over many bunches in a batch to get lower noise

22. Analog Filter Design is Complicated! • Tradeoffs between sharpness of frequency cutoff and propagation delay spread • Gaussian filter chosen here for no good reason • Echotek board uses hybrid lowpass filter module from Mini-circuits. Is this what we want? Cutoff is Sharper than Gaussian

23. “Universal BPM” Signal ProcessingStep #2: Analog-Digital Conversion What ADC Clock Speed is needed? • ~53 MHz Bandwidth limited signal, sampled by 106 MHz ADC, measures eitherin-phase (cosine) orquadrature (sine) component • but not both ==> ADC clock phasing matters! • 212 MHz sampling measures bothin-phaseandquadrature components. Phasing is not critical to determine vector magnitude.

24. In-Phase and Quadrature Sampling “A - B” gives bunch-by-bunch “in-phase” signal • This is the argument for sampling at 2x Nyquist “D - (C+E)/2” gives bunch-by-bunch “out-of-phase” quadrature signal Vector Sum sqrt(I**2 +Q**2) is insensitive to clock jitter

25. This ADC can sample 53 MHz signals at 4 samples per cycle to measure both In-Phase and Quadrature on each cycle

26. Synchronous vs. Asynchronous ADC Sampling • The choice is between N*53 MHz beam phase locked sampling, or asynchronous sampling at a (possibly) lower rate • Asynchronous sampling of a waveform will allow you to recover all the information, IF: • you know that the input is a pure sine wave, or • you know the input is repetitive (stored beam), or • the sampling rate is much higher than fMAX

27. The Perils of Undersamplinga Single-Pass Beam If a single-pass beam does not have uniform bunch populations, the ADC input is NOT a good sine wave and an undersampled waveform can give an erroneous picture of the beam signal. The signal CAN be reconstructed with many passes of stored beam.

28. Conclusions on ADC Clock Rate • A Universal BPM system must sample at 2-4x the maximum bunch frequency, depending on whether we want to guarantee the clock phase stays aligned or not. • You can never be: • too rich • too thin • or have too many ADC samples

29. “Universal BPM” Signal Processing:How Many ADC bits are needed? • Biggest Signal: Coalesced Proton Bunch • 350E9 particles in single ~10ns bunch • if bunch is shorter, doesn’t matter, filter will spread it • Smallest Signal: Antiproton Pilot Shot at 2.5 MHz • 10E9 particles/bunch in four ~50ns bunches • this gives ~25x smaller pulse height than same number of particles in 10ns bunch, but ~5x smaller pulse area • Off-center beam positions require an additional 4:1 dynamic range (maybe less with hybrid)

30. Biggest Signal in Main Injector Coalesced bunch puts ~350E9 in single 53MHz Bucket Bunch length will be ~3ns at transition with GPJ low emittance coalescing.

31. No guarantees on bunch populations or individual bunch transverse positions

32. ADC Dynamic Range(Main Injector, which is worst case) • Set up so 14 Bit ADC (16k counts) almost saturates for full scale hit from coalesced bunch (300E9) • Lose factor of 30 = (10E9/300E9) for bunch charge of Antiproton Pilot Shot • Lose Factor of 25 for pulse height of 50ns bunch vs. 10ns bunch ==> 21 counts per sample • Signal from 4-bunch pilot shot shows up in ~40 samples ==>800 counts if beam centered in BPM ADC bit noise is sub-mm contribution to resolution

33. “Universal BPM” Signal ProcessingStep #3: Digital Filter • Many Filters can operate in parallel in FPGA • single Bunch FIR filter (weighted sum of samples) • single Batch filter (53 MHz, 2.5 MHz, 7.5 Mhz) • Multi-pass averaging (can extract all harmonics of revolution frequency for stored beam) • Automatic peak-finding or calculation of I**2+Q**2 to make timing less critical • Waveform capture allows filters to be debugged & optimized & new versions tested offline

34. “Universal BPM” Signal ProcessingStep #4,5,6: Beam Position Signal 4) Calculate Sum & Difference of plate signals • Traditionally done in analog “Σ-Δ” Hybrid • This saves 1-3 bits of dynamic range for ADC • 14-bit ADC dynamic range OK without Hybrid 5) (Difference / Sum) gives position X ~ (Right - Left) / (Right + Left) 6) Linearization lookup table or polynomials (X,Y) CALIBRATED = F(XRAW, YRAW)

35. Main Injector BPM Response Map Linearization can be done in FPGA or readout software J. Crisp

36. “Universal BPM” Signal ProcessingStep #7: Averaging and Filtering Many Types of averaging possible: Position Averaging over Bunches in a Batch Multi-Turn Averaging of Positions Multi-turn averaging of Raw Signals Fitting to betatron frequency (injection errors) - this gives info for -function measurement Emulation of DDC chip functions Spectrum analysis of position & phase Different filters can be simultaneously active

37. Application #2: Generic Instrumentation Readout Scope What we want in a “Generic ‘Scope”: 1) Ability to trigger on TCLK events, Beam Synch Events, analog threshold crossings of different channels, etc. 2) Multiple Users Sharing without conflicts - separate copies of trigger logic - separate buffers to store captured signals - separate filter algorithms run simultaneously 3) Common hardware & software among systems

38. Example Application of Generic ‘Scope: Flying Wire PMT Readout 53 MHz, TCLK, MDAT,... PMT(s) in Tunnel 106 MHz FAST ADC Minimal Analog Filter Monster FPGA 14 FAST ADC Minimal Analog Filter CPU Bus VME/ VXI/ PCI/ PMC etc. FAST ADC Minimal Analog Filter Encoder Signals FAST ADC Minimal Analog Filter Motor Drive Motor DAC

39. Example Application of Generic ‘Scope: Flying Wire PMT Readout • Photomultiplier Tube (PMT) pulses presented to Analog filter to limit BW • Summing circuits in FPGA give total PMT pulse height in narrow and wide gates • Individual gates report signals for 36x36 or more bunches, average over many turns, etc. • FPGA can be used to control & trigger the fly • Raw PMT pulses can be simultaneously looked at via “multi-user” hooks

40. Application #3: Recycler / Injection Damper • Fixed revolution frequency simplifies design. • Measures position of each “bunch” on each pass, then kicks it back on center. • Same circuit usable for Injection Dampers, which also operate at fixed frequency. • Digital multi-turn filters used to calculate kick. • Narrow-band and Broad-band filters can run simultaneously on same device, if needed.

41. Analog Beam Damper SystemSimplified schematic of narrow band Transverse Damper for 53 MHz bunched beam McGinnis The Digital system can exactly emulate this, plus run other algorithms for various bunch structures. - Power Amp (Buy / Exists) Move from Analog to Digital Processing inside FPGA

42. “Recycler / Injection Damper”(same generic hardware) 53 MHz, TCLK, MDAT,... 106 MHz Stripline Pickup “A” FAST ADC Minimal Analog Filter Monster FPGA 14 FAST ADC Minimal Analog Filter CPU Bus VME/ VXI/ PCI/ PMC etc. OPTIONAL Pickup “B” FAST ADC Minimal Analog Filter FAST ADC Minimal Analog Filter Power Amp. Stripline Kicker 106 MHz FAST DAC > 27 MHz

43. Emulating a 53 MHz Analog Mixer /LPF ANALOG MIXER FILTER Impulse response 53 MHz sin Both circuits have identical impulse response, and identical sensitivity to 53 MHz clock noise 70 MHz LPF BPM LPF 53 MHz DIGITAL FILTER (FIR or IIR) Impulse response 53 MHz Clock 70 MHz LPF Digital Filter BPM ADC

44. Advantages of Digital Filters • Digital filter can also operate at multiple lower frequencies ...simultaneously if desired. • MI will not be blind at 2.5 and 7.5 MHz Beam • Digital filters more reproducible (=>spares!) • Re-use Standard hardware with new FPGA code • or same code with different filter coefficients • Inputs and Outputs clearly defined • filters can be developed & debugged offline

45. Signal Processing Steps forRecycler / Injection Damper Echotek Board 1) Bandwidth-Limit input signal to ~53 MHz 2) 14 Bit Digitization at 106 MHz or 212 MHz 3) Filter to get single-bunch signal 4) Sum & Difference of BPM plate signals 5) Multi turn orbit difference filter w/delay 6) Pickup Mixing for correct Betatron Phase 7) Pre-Emphasis for Kicker Amp & Cable 8) Power Amp for Kicker Inside FPGA Buy

46. Processing Beam Position Measurements to Calculate Kick • One or two beam pickups • One or many turns • Nasty problems: • kicker phase adjustments vs. machine tune • DC orbit offset rejection

47. 3 - Turn Filter • Damper kick is calculated from single BPM position reading on 3 successive turns. Arbitrary Betatron Phase of Kicker can be accommodated

48. HERA-P Damper uses a 3-turn Digital FIR Filter • Digital Bunch by Bunch @ 96ns Spacing • Immediate digitization following peak detection … a very attractive system for FNAL to copy... Klute, Kohaupt et. al. EPAC ‘96

49. Recycler / Injection Damper FPGA Logic(single pickup with 3-turn filter) Gain Balance Weighted Sum for Arbitrary Betatron Phase Pickup ADC FIR Filter 1-turn Delay 1-turn Delay 1-turn Delay 14 ADC Standard BPM Processing 3 - Turn Filter Power Amp. Stripline Kicker 106 MHz Optional Pre-compensation Filter for Cable DAC > 27 MHz

50. 3 Turn Filter Coefficients • Damper kick is weighted sum of beam positions on the 3 previous turns. • 3 Filter Coefficients Uniquely Determined by: • System Gain • Betatron Phase Desired at Kicker • Constraint that sum of filter coefficients = 0 (so that filter does not respond to DC offsets.)