SoftGlue : A Run-Time User-Configurable FPGA in EPICS

1. SoftGlue:A Run-Time User-Configurable FPGA in EPICS Tim Mooney Kurt Goetze Advanced Photon Source / Engineering Support EPICS Collaboration Meeting - October 2010 - Brookhaven National Laboratory The submitted manuscript has been created by UChicago Argonne, LLC, Operator of Argonne National Laboratory (“Argonne”). Argonne, a U.S. Department of Energy Office of Science laboratory, is operated under Contract No. DE-AC02-06CH11357. The U.S. Government retains for itself, and others acting on its behalf, a paid-up nonexclusive, irrevocable worldwide license in said article to reproduce, prepare derivative works, distribute copies to the public, and perform publicly and display publicly, by or on behalf of the Government.

2. (software configurable Glue electronics) softGlue User-programmable digital electronics

3. softGlue: at a glance • Fixed collection of digital logic elements • Gates, counters, flip-flops, etc. • Loaded into FPGA at boot time • Programmable connection to field I/O • Logic is “wired” by the values of EPICS PVs: Same name: connected (* means “invert”)

4. softGlue: EPICS API • EPICS records, clients can also read and write logic/parameter values directly: Logic value Parameter

5. softGlue: field I/O • Software configurable digital I/O • 48-bit TTL (or 24-bit RS-422, LVDS, etc.) • I/O direction specified at boot time • Safe, run-time modifiable, interrupt dispatch: • On rising edge • On falling edge • On both • On neither

6. softGlue: FPGA content • Typical collection of electronics elements:

7. softGlue: FPGA content • 4 AND gates • 4 OR gates • 4 Buffers • 2 XOR gates • 48 field outputs • 48 field inputs • 4 Down counters • 4 Up counters • 4 Divide-by-Ns • 4 D Flipflops • 2 Multiplexers • 2 Demultiplexers

8. softGlue: requirements • IndustryPack carrier board • Acromag IP-EP201 FPGA module • Field I/O breakout hardware • 50-pin ribbon connector • softGlue EPICS software module • http://www.aps.anl.gov/bcda/synApps/softGlue/softGlue.html • softGlue module requires ASYN, IPAC, and CALC

9. softGlue: pros and cons Advantages • Hardware in close coordination with EPICS software • Software and hardware in same repository • Easy to distribute/install hardware • Autosave user configured circuitry Limitations • Only 15 “wires” (signal names) • Field I/O signals are not maintained during reboot • IP-EP201 field I/O is unsuitable for high-frequency signals • unterminated, shared ground • Other IP-EP20x not yet tested

10. softGlue: tested applications • Digital I/O • With no programming, softGlue functions as 48-bit I/O • Coordinate digital electronic devices • Drive shutters, detectors from motor step pulses • Disable data acquisition during motor accel/decel • Trigger EPICS software on complex I/O events • While A and B, process record on falling edge of C • Programmable time base for EPICS software • Process record in 400 μs • Smart oscilloscope trigger • Trigger when A rises after and within 50 μs of B

11. softGlue: implementation • The basic idea, schematically: EPICS PV EPICS PV FPGA

12. softGlue: implementation • Asyn driver • Programs FPGA from .hex file • Writes to registers implemented in FPGA • Asyn device support • Standard support for parameter values • Custom string support implements signals • EPICS database • Polls signals • Marks connected signals for display • MEDM display files, autosave/BURT request files

13. softGlue: credits • Eric Norum – IndustryPack Bridge (interfaces FPGA components to IP/VME bus) • Marty Smith – EPICS driver, field I/O FPGA • Kurt Goetze – FPGA content • Tim Mooney – EPICS application The cast, in order of appearance: