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zero suppression with APVDAQ

zero suppression with APVDAQ . 2012/02/07 SVDPXD meeting Seoul National Univ , Changwoo Joo. Introduction. We are developing APVDAQ in J-PARC With our DAQ, event rate is eight APVDAQ => up to ~20Hz Four APVDAQ => up to ~60Hz We’d like to increase event rate of APVDAQ.

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zero suppression with APVDAQ

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  1. zero suppression with APVDAQ 2012/02/07 SVDPXD meeting Seoul National Univ, ChangwooJoo

  2. Introduction • We are developing APVDAQ in J-PARC • With our DAQ, event rate is • eight APVDAQ => up to ~20Hz • Four APVDAQ => up to ~60Hz • We’d like to increase event rate of APVDAQ. • There is bottle neck of data from VME to PC • Data transfer time • Apv25=>VME : ~200 us • VME=>PC : ~dozens ms

  3. Zero Suppression (ZS) • Build up FPGA firmware level data suppression • Put ZS block between data pipe line and FIFO ZS block apv25 data FIFO (Memory) To PC

  4. ZS block - inside

  5. ZS block - algorithm • Because of sensor configuration, ZS block can handle 3 apv25 chips 6 sampling mode. => We can adjust it. • ZS process (it takes ~86us) • 1. Save data from apv25 chip • 2. Find hit channel • 3. Send hit channel data to FIFO (memory) • How to find hit? • ZS block generates T value for each channel T = ADC height of 2nd sample – pedestal of 2nd sample + (3nd sample) + (4th sample) + (5th sample) And then compares T with threshold to find hit channel • ZS block needs calibration run for pedestal and threshold. • Standard deviation of T in calibration run is unit of threshold. (Ts)

  6. ZS FPGA Test Get [ZS data] and [unZS data] of same event with 2 sigma threshold, forced trigger. ZS by FPGA ZS by PC Compare No error for ~20000 events

  7. Test experiment in RCNP OSAKA • SSD sensor • ~290um thick • ~78um strip pitch • ~6x6cm2effective area

  8. Result – hit pattern PMT trigger Up stream (SSDA, B) Down stream (SSDC, D) Strip pitch is ~78um, total 768 strips. ~6cm x 6cm window. No big difference between unsuppressed, ZS data.

  9. Result – hit pattern MPPC trigger Up stream (SSDA, B) Down stream (SSDC, D) Strip pitch is ~78um, total 768 strips. ~6cm x 6cm window. No big difference between unsuppressed, ZS data.

  10. Result – analysis parameter • I’d like show the comparison between unsuppressed data and ZS data. • Result shows 7 runs. 3 unsuppressed and 4 ZS data. • Each run has ~5000 events. • Scin : scintillator + PMT trigger • MPPC : multi pixel photon counter trigger • Beam rate counted by PMT1 • Un : unsuppressed data • ZS : suppressed data • number : threshold (standard dev of T distribution) Trigger Beam rate Data

  11. Result – efficiency Trigger Beam rate Data

  12. Result – Signal Noise Ratio (SNR) Trigger Beam rate Data

  13. Result – Time resolution Trigger Beam rate Data

  14. Result – Time resolution condition • Time resolution analysis condition • Cut out unreasonable fitting parameter • Cluster width is less than three • Cut out Bad timing signal • We had bad beam and trigger • Fake trigger due to signal reflection. • We got several cycles of beam. • Eventually we got off timing beam. • We lost 20~30% of event in analysis

  15. Result – Data size • Because ZS block sends data of hit channel only, data size is dynamic . => ZS data size • In analysis, we pick up real hit channel from ZS data => Rhitdata size • We want to check average and stabilityof data size

  16. Result – Average of data size 100% 100% 100% Trigger Beam rate Data

  17. Calibration – off beam on beam • We had mistake running calibration with beam. • It explains 3% eff drop of MPPC, 1.7MHz, ZS run • Still we can believe analysis result because we used low threshold and T value. (We use off beam calibration result for analysis)

  18. Conclusion • We try to increase event rate of APVDAQ with data suppression by FPGA firmware development. • We confirmed ZS with noise run. • We had test experiment with proton beam. • Analysis result of suppressed data is similar with unsuppressed data one. • Suppression rate is 2~6% of original data size. => We can suppress more. (Rhit size ~0.4%) • We had beam, trigger, calibration problem => But ZS itself works well.

  19. Back up

  20. Signal analysis adcch Y = p0(X - p1)exp( -(X-p1)/p2 ) nsec

  21. Algoritm – ZS block ebit correction

  22. Calibration – off beam on beam • We had mistake running on beam calibration. • It explains 3% eff drop of MPPC, 1.7MHz, ZS run • Still we can believe analysis result because we used low threshold and T value. Beam off Beam on Calibration Run01 Run02 Run03 Cal Run01 Cal Run02 Cal Run03

  23. Introduction • Data suppression - FPGA code - Algorithm • Test experiment - set up and beam - result - calibration • Conclusion

  24. Our Goal We are developing APVDAQ for higher event rate.

  25. Event rate of APVDAQ Four APVDAQ => up to 70Hz One APVDAQ => up to 340Hz Expected trigger rate is ~30kHz in SuperB DAQ event rate is ~300Hz in J-PARC(K1.8)

  26. Algoritm – ZS block step 3 • Send marked channel data to FIFO • Example 1 | 16 | 358 | 746 2 | 16 | 412 | 228 3 | 16 | 403 | 713 4 | 16 | 390 | 723 5 | 16 | 368 | 732 6 | 16 | 356 | 232

  27. Introduction – data • There is bottle neck of data from VME to PC • Data transfer time • Apv25=>VME : ~200 us • VME=>PC : ~dozens ms • But we don’t need data of whole 128 channels • We need pedestal, adc height sample #, channel #, chip # of hit channel • Usually one event has 1~3 hit channels/sensor

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