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Fig . 13.3 Definitions of propagation delays and switching times of the logic inverter.

Fig . 13 . 2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points. Fig . 13.3 Definitions of propagation delays and switching times of the logic inverter.

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Fig . 13.3 Definitions of propagation delays and switching times of the logic inverter.

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  1. Fig. 13.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

  2. Fig. 13.3 Definitions of propagation delays and switching times of the logic inverter.

  3. Fig. 13.4(a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

  4. Fig. 13.5 The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched.

  5. Fig. 13.12 A two-input CMOS NOR gate.

  6. Fig. 13.13 A two-input CMOS NAND gate.

  7. Fig. 13.16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) rations of QN and QP, respectively, of the basic inverter.

  8. Fig. 13.17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) rations of QN and QP, respectively, of the basic inverter.

  9. Fig. 13.21 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5, Vtn = -Vtp = 1 V, and r = 9.

  10. Fig. 13.33(a) basic structure of dynamic-MOS logic circuits; (b) waveform of the clock needed to operate the dynamic-logic circuit; and (c) an example circuit.

  11. Fig. 13.34(a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge-sharing problem at the expense of static-power dissipation.

  12. Fig. 13.35 Two single-input dynamic-logic gates connected in cascade. With the input A high, during the evaluation phase CL2 will partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction.

  13. Fig. 13.37(a) Two single-input DOMINO CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.

  14. Fig. 13.38(a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point of the latch.

  15. Fig. 13.40 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by .

  16. Fig. 13.42 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory chips.

  17. Fig. 13.44 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase nonoverlapping clock whose waveforms are shown in (b).

  18. Fig. 13.45(a) A master-slave D flip-flop. Note that the switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required.

  19. Fig. 13.47 Monostable circuit using CMOS NOR gates. Signal source vI supplies the trigger pulses.

  20. Fig. 13.50 Timing diagram for the monostable circuit in Fig.13.47.

  21. Fig. 13.52(a) A simple astable multivibrator circuit using CMOS gates. (b) Waveforms for the astable circuit in (a). The diodes at the gate input are assumed ideal and thus limit the voltage vI1 to 0 and VDD.

  22. Fig. 13.53(a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/(6tp).

  23. Fig. 13.54 A 2M+N-bit memory chip organized as an array of 2M rows x 2N columns.

  24. Fig. 13.55 A CMOS SRAM memory cell.

  25. Fig. 13.60 A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which can utilize both B and B lines). DRAMs can be turned into differential circuits by using the “dummy cell” arrangement shown in Fig.13.61.

  26. Fig. 13.61 Waveforms of vB before and after activating the sense amplifier. In a read-1 operation, the sense amplifier causes the initial small increment V(1) to grow exponentially to VDD. In a read-0 operation, the negative V(0) grows to 0. Complementary signal waveforms develop on the B line.

  27. Fig. 13.62 Arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.

  28. Fig. 13.63 A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.

  29. Fig. 13.64 A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.

  30. Fig. 13.65 A free column decoder. Note that the colored path shows the transistors that are conducting when A0 = 1, A1 = 0, and A2 = 1, the address that results in connecting B5 to the data line.

  31. Fig. 13.66 A simple MOS ROM organized as 8 words x 4 bits.

  32. Fig. 13.67 (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.

  33. Fig. 13.68 Illustrating the shift in the iD-vGS characteristic of a floating-gate transistor as a result of programming.

  34. Fig. 13.69 The floating-gate transistor during programming.

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