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MVT Read-Out Architecture & MVT / SVT Integration Issues

MVT Read-Out Architecture & MVT / SVT Integration Issues. Irakli MANDJAVIDZE DAPNIA, CEA Saclay, 91191 Gif-sur-Yvette, France. Overview. MVT Readout Number of Channels Architectural considerations Front End Unit Back End Unit Data Rate Estimations SVT / MVT Integration

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MVT Read-Out Architecture & MVT / SVT Integration Issues

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  1. MVT Read-Out Architecture &MVT / SVT Integration Issues Irakli MANDJAVIDZE DAPNIA, CEA Saclay,91191 Gif-sur-Yvette, France Irakli.MANDJAVIDZE@cea.fr

  2. Overview • MVT Readout • Number of Channels • Architectural considerations • Front End Unit • Back End Unit • Data Rate Estimations • SVT / MVT Integration • Number of SVT and MVT Channels • Some comparisons • Specific and common readout parts Irakli.MANDJAVIDZE@cea.fr

  3. Number of MVT Channels • Number of MMs • Barrel X: 3 views x 3 MMs = 9 • Barrel Y: 3 views x 3 MMs = 9 • Forward: 3 stations x 2 views x 6 MMs = 36 • Total: 54 • Number of channels • Barrel X: ~10 000 • Barrel Y: ~11 000 • Forward: ~25 000 • Total: ~46 000 Irakli.MANDJAVIDZE@cea.fr

  4. MVT Read-out Architectural Considerations • Minimal number of different hardware to develop and maintain • front end cards • back end concentrator cards • Partitioning: DAQ Read-out Unit = View • Single communication channel with DAQ per View • Concentrate data from all MM in a View before sending to DAQ Irakli.MANDJAVIDZE@cea.fr

  5. MVT Read-out Architectural ConsiderationsA DAQ Readout Unit FEU FEU(shaping,AD conversion,compression) FEU ... ... ... • One read-out unit per view On-detector Off-detector Counting Room Readout Links(ROL) Back End Units(BEU) FE links(FEL) FE Units(FEU) Trigger Link (?)← Clock← Trigger← Fast commands→ Fast status BEU(control,concentration) DAQ Link (Ethernet)→ Data↔ Slow Control Bi-dir Optical Fiber← Clock← Trigger→ Data↔ Control / status FLEX cable→ Signals Irakli.MANDJAVIDZE@cea.fr

  6. MVT Read-out Architectural Considerations:Partitioning 3W 3V 2W 2V 1V 1W 2Y 2X 1Y 1X 3Y 3X • 12 MVT partitions Trigger / DAQ B A R R E L F O R W A R D Irakli.MANDJAVIDZE@cea.fr

  7. Read-out Architecture Considerations: Front End Unit (FEU) 64-Channel connectors 64 (128)-cannel ASICs 8- (4-)channelFADC CtrlFPGA E/OTx/Rx • 64 channels per FLEX • 64- or 128-channel FE ASIC • FEU6 option: • 6 64-channel FLEXes • 384 channels • 6 or 3 ASICs • an 8- or 4-channel FADC • a controller FPGA • an optical link towards a concentrator card Irakli.MANDJAVIDZE@cea.fr

  8. Read-out Architecture Considerations:FE Granularity • Barrel X with 3 MM / view • D1X: 6 FEU (2 FEU / MM) • D2X: 9 FEU (3 FEU / MM) • D3X: 12 FEU (4 FEU / MM) • Barrel Y with 3 MM / view • D1Y: 6 FEU (2 FEU / MM) • D2Y: 9 FEU (3 FEU / MM) • D3Y: 12 FEU (4 FEU / MM) • Forward with 6 MM / view • Disk: 12 FEU (2 FEU / MM) • Total number of FEUs: 126 • 756 64-channel ASICs or 378 128-channel ASICs • 756 64-channel FLEXes Irakli.MANDJAVIDZE@cea.fr

  9. Read-out Granularity:Back End Unit (BEU) BEU EthernetDAQSlow Controllink TriggerClockFast Controllink • Functionality • Receives CLAS12 clock, trigger and control flow & distributes it to all FEUs of a view • Concentrates data from the FEUs & sends them to DAQ • BEU12 option: • 12 optical FEU links • Ethernet DAQ – Slow Control link • Trigger – Clock – Fast Control link • whatever standard • Form factor? • Total of 12 BEUs needed Irakli.MANDJAVIDZE@cea.fr

  10. Read-out Granularity:Barrel X,Y and Forward V, W Units F1V, F2V, F3VF1W, F2W, F3W B1X, B1Y B2X, B2Y B3X, B3Y BEU BEU BEU BEU MM1 FEU MM1 MM1 MM1 MM2 MM3 MM2 MM2 MM2 MM4 MM5 MM3 MM3 MM3 MM6 Irakli.MANDJAVIDZE@cea.fr

  11. Data Rate Estimations • Hypothesis • 10 MHz Barrel background (safety factor ~2) • 20 MHz Forward background (safety factor ~1.4) • 20 kHz L1 rate (safety factor 2) • Multiplicity: barrel 4, forward 1.2 • 20 MHz sampling rate • 4 samples / channel read-out • Full readout: 7400 Mbyte/s • Event size 380 Kbyte • Zero suppression: 75 Mbyte/s • Subtract common noise, apply threshold • Event size 3.8 Kbyte • Data reduction factor of ~100 Irakli.MANDJAVIDZE@cea.fr

  12. Number of SVT ChannelsSpeculations • 3 Regions • 2 views per region • Regions composed of 256-channel modules • Region 1: 8 modules • Region 2: 12 modules • Region 3: 16 modules • Number of channels • Region 1: 4096 • Region 2: 6144 • Region 3: 8192 • Total: ~18 000 • ~140 additional 128-channel ASICs Irakli.MANDJAVIDZE@cea.fr

  13. Current Ideas: SVT • On-detector front-end electronics • relatively stringent space & power constraints • Space • ASIC • wire-bonded • minimal number of external components • as complete read-out system as possible • higher channel count • cooling extends up to detector • Power • minimize mW / channel ratio • special attention to low voltage distribution Irakli.MANDJAVIDZE@cea.fr

  14. Current Ideas: MVT • Off-detector front-end electronics • looser space & power constraints • Space • ASIC • packaged • more complex read-out circuitry possible • external digitization, zero suppression • lower channel count • cooling system does not extend to detector • Power • can permit somewhat higher mW / channel ratio • low voltage is not distributed to detector Irakli.MANDJAVIDZE@cea.fr

  15. Common Readout FPGA FPGA E/O E/O ... On-detector Off-detector Counting Room • An external FADC: additional 1 mW / channel (at least) Common ReadoutController(CROC) MVT FEU TriggerFast control ASIC PROTECT FLEX BackendUnit MM ADC ROL CONNECT Opticallink DataSlow control CROC TriggerFast control SVTmodule (doublelayer) ASIC Readout Link(ROL) BackendUnit ADC Opticallink LVDS DataSlow control Irakli.MANDJAVIDZE@cea.fr

  16. Data Rate Estimations:SVT Speculations • Hypothesis • 30 MHz background (safety factor ~?) • 20 kHz L1 rate (safety factor 2) • Multiplicity: 1.2 (?) • 20 MHz sampling rate • 4 samples / channel read-out • Full readout: 2800 Mbyte/s • Event size 144 Kbyte • Zero suppression: 19 Mbyte/s • Subtract common noise, apply threshold • Event size 1 Kbyte • Data reduction factor > 100 Irakli.MANDJAVIDZE@cea.fr

  17. Discussions • MVT participation in L1 Trigger is not envisaged • What is the control interface? • clock and trigger distribution • Current FE electronics volume estimates: 0.12 m3 • a cube of 50 cm! • central SVT / MVT Tracker – 0.1 m3 • What are the space constraints? • how do the SVT and MVT on-detector infrastructures cohabitate? • how do they cohabitate with other central detectors? • power, cables, channel protections, electronics, cooling • What can be common? • ASIC? • read-out controller & back-end concentrator? • What if the SVT electronics could be off-detector? The most optimal read-out granularity and partitioning will be defined accordingly Irakli.MANDJAVIDZE@cea.fr

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