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USB Adapter for Experiment Board

USB Adapter for Experiment Board. Created By : Itai Heller Ofir Asulin Supervised By: Mony Orbach. Project Goals. Enhancing & Expanding an existing prototype circuit built on a wire-wrap board. Manufacturing a printed circuit in order to broaden and

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USB Adapter for Experiment Board

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  1. USB Adapter for Experiment Board Created By : Itai Heller Ofir Asulin Supervised By: Mony Orbach

  2. Project Goals • Enhancing & Expanding an existing prototype circuit built on • a wire-wrap board. • Manufacturing a printed circuit in order to broaden and • improve lab experiments, adding future implementations. • The prototype is a Communication adapter designed to • connect between a PC USB Port and a Lab Experiment boards.

  3. Existing Environment • The current device is based upon an old 8031 micro-controller with a RS-232 communication protocol. • It is necessary to advance to a more modern communication protocol in order to keep up with the PC advance, furthermore a higher data-flow rate is needed for future implementations. • The new interface must be consistent with existing environment in the lab (PC , 6 types of lab experiment devices and windows XP with VB 6.0).

  4. Characterization of system Inputs i) Type of the lab educational device: received on installation (8bit). ii) Number of lab educational device: received from device (8 bit). iii) Random address: received from the PC (3 bit). Future implementations: iv) input Port: (8 bit )

  5. Characterization of system Outputs i) PC’s approval for the connection with the device: On screen. ii) Approval for the receiving of the random address: Buzzer (1 bit). Future implementations: iii) output Port (8 bit)

  6. 3 bits Experiment Board (Midgam) Confirmation (Buzzer) 1 bit PC DLP USB Adaptor Cyclone FPGA USB 3 bits Draw Control Clock EPSC 1 bit Reset 8 bits 8 bits 8 bits Outside Voltage Power Stabilizer Board Number I/O PORT LM1085 2XSwitch DIP-8 Block Diagram

  7. Currents and Voltages • The system is supplied with 3 main voltages: • 5 [v] through the USB adaptor from the PC. • 12 [v] from the experiment board is converted to 5 [v] by an internal regulator (LM1085). • 5 [v] from the internal regulator that are converted to 3.3 [v] and 1.5 [v] by Two internal regulators (LM1085-3_3TO263 and LM1085-ADJTO263). • Ground is received from the PC and experiment board. • The limitations on the systems currents are: • 500 [mA] (for the 5 [v] power supply from the PC) • 2 [A] (for the three internal regulators).

  8. Voltage usage • 5 [v] (that were converted from 12 [v] by LM1085) are used by the: • Buzzer. • Relay. • Switches. • 3.3 [v] (that were converted from 5 [v] by LM1085-3_3) are used by the: • Cyclone for VCCIO. • Transceivers. • DLP for VCCIO. • 1.5 [v] (that were converted from 5 [v] by LM1085-ADJ) are used by the: • Cyclone for VCCINT. • 5 [v] (that are received from the PC via the USB) are used by the: • Transceivers. • DLP.

  9. FPGA Logical Tasks • The FPGA receives and stores a raffled number from the PC. • It Initiates the Draw Control so that the experiment board can start its raffle. • The FPGA compares between the two raffled numbers. • If the two numbers equal than the FPGA activates the Buzzer. If the numbers do not equal the FPGA initiates the experiment board again so it will start a new raffle, this is repeated until an equation is achieved.

  10. 8 Bit I/O Port • 16 Pin Port. • 8Bit i/o data. • FIFO Protocol. • rd, wr, rx, tx, clk & resetcontrol lines. • Vcc(3.3v) , GND power lines.

  11. Initialization of the PCB • The system is shut down, When the main power switch is off, and the USB cable is not connected. • The control lines between the FPGA and the DLP are connected to Pull-Up and Pull-Down resistors to prevent High-Z. • The transceivers are not accessible until the FPGA completes its initialization. • By connecting the USB and switching on the main power on, the following occurs: • The FPGA uploads its software from the EPCS. • The DLP is disconnected from the PC (RESET=‘0’) until the FPGA grants it access to the PC. • When the FPGA finishes its initialization, appropriate values are set at its control line. The transceivers are opened and set to their appropriate data flow. • The DLP is connected to the PC (RESET=‘1’), and the RESETO signal of the DLP indicates this. • System ready to begin the experiment.

  12. Schedule • Theoretical orientation.6/4/2005-DONE • System planning:12/5/2005-DONE • Choosing and placing of components • Learning Orcad • Circuit drawing on Orcad and handing it to Ella.-DONE • Creating the circuit (with Ella) and configuration of the FPGA (in VHDL).12/6/2005 • Simulations & Debugging.12/7/2005 • Driver Writing.28/7/2005 • Implementation of the Adaptor with the experiment system.28/8/2005

  13. Datasheet Links • LM1085 converter • Cyclone-FPGA • DLP-USB Adaptor • CMOS Octal Latch • Transceivers

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