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October 11, 2000

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October 11, 2000

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    1. October 11, 2000 1

    2. October 11, 2000 2

    3. October 11, 2000 3 USB 2.0 Transceiver Macrocell Interface Overview

    4. October 11, 2000 4 Macrocell Requirements Enable Peripherals Does not address hubs and hosts No downstream port support Disconnect Detection 40 bit EOP No repeater support Very implementation dependent Requires separate port

    5. October 11, 2000 5 Macrocell Requirements Simplify the design process for peripheral vendors Consolidate high speed logic in to a discrete module Provide a “standard” USB 2.0 hardware interface Minimize time to market Isolate process dependent transceiver development Enable standard library elements from ASIC vendors Peripheral vendors can focus on product specific development Easy port of existing USB 1.1 SIE logic

    6. October 11, 2000 6 USB Device Development Assumptions Prototyping FPGA + UTMI Compliant Discrete Transceiver Production Low Volume Gate Array + UTMI Compliant Discrete Transceiver High Volume ASIC + integrated UTMI Compliant Transceiver Macrocell

    7. October 11, 2000 7 Device Anatomy USB Transceiver Macrocell (UTM) Serial Interface Engine Device Specific Logic

    8. October 11, 2000 8 Serial Interface Engine SIE Control Logic USB Transaction State Machine PID, Address, and EP match logic Checks receive completion status Chains packets into transactions Endpoint Logic FIFOs and FIFO control

    9. October 11, 2000 9 Transceiver Macrocell Converts USB signaling into a parallel interface USB 2.0 compliant serial interface Multiple Parallel Data Interface Options Multiple Speed Options HS/FS, FS Only, LS Only

    10. October 11, 2000 10 Macrocell Functions HS and FS signaling and termination HS receiver squelch USB clock recovery Bit stuffing NRZI encoding Serializing and deserializing Data-rate tolerance Data buffering Single interface for HS/FS, FS or LS operation

    11. October 11, 2000 11 Block Diagram

    12. October 11, 2000 12 Interface Features Packet Engine Automatically handles SYNC Pattern and EOP Flow Control Compensates for Bit Stuffing and Data Rate Tolerance Complete Primitives for Full Protocol Support Speed Switching Clock Generation Power Control

    13. October 11, 2000 13 Interface Options Integrated Macrocell 8-Bit Uni-directional 16-Bit Uni-directional Discrete Transceiver 8-Bit Bi-directional 16-Bit Bi-directional / 8-Bit Uni-directional

    14. October 11, 2000 14 8-Bit Uni-Directional

    15. October 11, 2000 15 16-Bit Uni-Directional

    16. October 11, 2000 16 8-Bit Bi-Directional TXValid Determines data direction

    17. October 11, 2000 17 16-Bit Bi-Directional ValidH provides multiplexed high-byte valid flag

    18. October 11, 2000 18 Protocol Primitive Support Resume Assertion Resume Detection Suspend Detection Reset Detection HS Detection Handshake

    19. October 11, 2000 19 Clock Generation Macrocell supplies clocks to the SIE Frequency depends on implementation HS/FS 60 MHz 8-bit uni-directional 30 MHz 16-bit uni- or bi-directional FS Only 48 MHz 8-bit uni-directional LS Only 6 MHz 8-bit uni-directional

    20. October 11, 2000 20 Power Control SuspendM signal Shuts down clocks Maintains terminations Vendor determined Drive Current Control Enabled during transmits Enabled by receives Always on

    21. October 11, 2000 21 USB 2.0 Transceiver Macrocell Interface Testing

    22. October 11, 2000 22 Testing UTMI Test Connector Specification Test Environment - 3 board set Off the shelf i960 eval board Custom SIE card FPGA, DPRAM, and Test Points Daughter Card with UTMI Transceiver Functionality Packet Blaster Single Packet operations Device Emulator Transaction level operations

    23. October 11, 2000 23 UTMI Test Connector Specification UTMI Test Connector 100 Pins Electrical interface Timing Levels Mechanical design PCB layout

    24. October 11, 2000 24 Board Set Processor Card EVAL80960VH Evaluation Platform Board RAM, ROM, FLASH, Serial Port FPGA Card Dual Port RAM - 64KB FPGA - Quicklogic Test Points Transceiver Daughter Card Discrete UTMI compliant transceiver Custom circuitry

    25. October 11, 2000 25 Block Diagram

    26. October 11, 2000 26 Mechanicals

    27. October 11, 2000 27 Pinout Features Vendor Status and Vendor Control support Multiple Datapath Options Supported 8-Bit Bi-Directional 8-Bit Uni-Directional 16-Bit Bi-Directional/8-Bit Uni-Directional Vendor ID 13 General Purpose I/O pins Vbus Control

    28. October 11, 2000 28 Pinout

    29. October 11, 2000 29 Next Steps Get the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification http://developer.intel.com/technology/usb/ No Royalty Design to the UTMI Specification Get the UTMI Test Connector Specification http://developer.intel.com/technology/usb/ Get your ASIC vendors to provide a UTMI Compliant Macrocells

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