Instruction-Level Parallelism dynamic scheduling

1. Instruction-Level Parallelismdynamic scheduling prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University Instruction-Level Parallelism 2

2. Dynamic Scheduling • Dynamic Scheduling rearranges instruction execution to reduce the stalls while maintaining data flow and exception behavior. • Enables handling some cases when dependences are unknown at compile time (e.g. memory reference). • Simplifiesthe compiler. • Allows the processor to tolerate cache misses delays by executing other code while waiting for miss resolution. • Allows code compiled with for one pipeline to run efficiently on a different pipeline. • Requires significant increase in hardware complexity. Instruction-Level Parallelism 2

3. In ordinary pipeline instructions are in-line issued and executed. • Ifan instruction is stalled in the pipeline, no later instructions can proceed. • If instruction jdepends on instruction i, all instructions after jmust be stalled until iis finished and jcan execute. SUB.D cannot execute because ADD.D dependence on DIV.D causes stall. Yet SUB.D is not dependent on anything in the pipeline. To execute SUB.D we separate instruction issue (at ID) into two parts: checking for hazards and waiting for the absence of a data hazard. Instruction-Level Parallelism 2

4. Out-Of-Order Execution Instruction are still in-order issued, but begin execution as soon as its data operands are available. Such a pipeline does out-of-order (OOO) execution, implying out-of-order completion. OOO introduces possibilities of WAR and WAW hazards, not existing in in-order pipeline. ADD.D and SUB.D are anti dependent. Executing SUB.D before ADD.D (waiting for DIV.D) violates the anti dependence, yielding a WAR hazard. Instruction-Level Parallelism 2

5. Likewise, to avoid violating output dependences of F6 by MUL.D, WAW hazards must be handled. register renaming avoids these hazards. • OOO completion must preserve exception behavior such that exactlyas by in-order. • No instruction generates an exception until the processor knows that that instruction raising the exception will be executed. OOO splits the ID stage into two stages: Issue—Decode instructions, check for structural hazards. Read operands—Wait until no data hazards, then read operands. Instruction-Level Parallelism 2

6. An IF stage preceding issue stagefetches either into an instruction register or a pending instructions queue. The EX stage follows the read operands stageand may take multiple cycles, dependingon the operation. • The pipelineallows multiple instructions simultaneously executed. • Without that a major advantage of OOO is lost. • Requires multiple functional units. Instructions are issues in-order, but can enter execution out of order. There are two OOO techniques: scoreboardingand Tomasulo’s algorithm. Instruction-Level Parallelism 2