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Design a bipolar differential amplifier stage while considering lithography variance and input voltage asymmetry. Achieve high matching performance and specified gain with low quiescent current consumption. Use detailed specifications and transistor parameters for optimal performance.
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NNAI – practice L2 BJT differential amplifier
Main parameters of used transistors: NPN: Is = 2.10-16 A • = 100 Output characteristic slope in active region = 0.5 μA/V at Ic=30uA (VE=60V) PNP: Is = 2.10-16 A = 50 Output characteristic slope in active region 1 μA/V při Ic=30uA (VE=30V) Nore: precise VTforT=300K is25.851241 mV Spice models can be find at http://www.umel.feec.vutbr.cz/~prokop/MNAI/MNAI.htm
Need of matching !!!!! Variance of the „hipo“ R over process and temperature in AMIS CMOS07: Rhipotyp = 2000 Ω/□ Rhipomin = 1600 Ω/□ Rhipomax= 2400 Ω/□ tc1 = -21.10-4 tc2 = 5.10-6 Variance Rhipo [Ω/□] pro t = (0-90)°C
Design bipolar differential stage with transconductance gm: 1
Determine input voltage asymmetry of the BJT differential stage knowing that due to the lithography variance the ratio of the BJT emitter areas is 1,1. means: Is1 = 1.1 Is2 Make sure the input offset is not ISS dependent… 2
Design differential output amplifier and gain A=10 Its quiescent current consumption is 40μA. VC = 5V -suppose Vbe = 0.65V 3
To satisfy demand of current consumption For voltage GAIN: Simulation PSpice 3
