14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 11: Microprogramming

1. 14:332:331Computer Architecture and Assembly LanguageSpring 2006Week 11: Microprogramming [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

2. Simplifying Control Design • For an implementation of the full MIPS ISA • instructions can take from 1 clock cycle to 20 clock cycles • resulting in finite state machines with hundreds to thousands of states with even more arcs (state sequences) • Graphical representations become impossibly complex • Instead, represent the set of control signals that are asserted during a state as a low-level control “instruction” to be executed by the datapath microinstructions • “Executing” the microinstruction is equivalent to asserting the control signals specified by the microinstruction

3. Microprogramming • Microinstruction has to specify • what control signals should be asserted • what microinstruction should be executed next • Each microinstruction corresponds to one state in the FSM and is assigned a state number (or “address”) • Sequential behavior – increment the state (address) of the current microinstruction to get to the state (address) of the next • Jump to the microinstruction that begins execution of the next MIPS instruction (state 0) • Branch to a microinstruction based on control unit input using dispatch tables • need one for microinstructions following state 1 • need another for microinstructions following state 2 • The set of microinstructions that define a MPS assembly language instruction (macroinstruction) is its microroutine

4. Defining a Microinstruction Format • Format – the fields of the microinstruction and the control signals that are affected by each field • control signals specified by a field usually have functions that are related • format is chosen to simplify the representation and to make it difficult to write inconsistent microinstructions • i.e., that allow a given control signal be set to two different values • Make each field of the microinstruction responsible for specifying a nonoverlapping set of control signals • signals that are never asserted simultaneously may share the same field • seven fields for our simple machine • ALU control; SRC1; SRC2; Register control; Memory; PCWrite control; Sequencing

5. MDR Review: Multicycle Data and Control Path PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control FSM ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

6. Review: Multicycle RTL Summary

7. Our Microinstruction Format

8. Our Microinstruction Format, con’t

9. Dispatch (Branch) Logic • Dispatch operations are implemented using special logic (PLAs)

10. compute PC + 4 fetch instr into IR write ALU output into PC go to instr 1 Creating the Microprogram • Fetch microinstruction • Label field represents the state (address) of the microinstruction • Fetch microinstruction assigned state (address) 0

11. use dispatch table in ROM_1 to choose next instr compute branch target (PC + sign_ext(IR[15-0])<<2)) and store it in ALUOut use rs and rt to read RegFile and store output in A and B Creating the Microprogram, con’t • Decode microinstruction • Decode microinstruction assigned state (address) 1

12. compute memory address (RegFile(rs) + sign_ext(IR[15-0])) and store it in ALUOut on lw – first read memory at ALUOut and store output in MDR; then write MDR into RegFile at rt on sw – write B into memory at address in ALUOut Creating the Microprogram, con’t • Memory-reference (lw & sw) microinstructions • Assigned states (addresses) 2, 3, 4, and 5

13. when done, go to fetch cycle for next instruction perform the ALU operation specified in the instr. function field using contents of A and B and store the result in ALUOut write ALUOut in the RegFile at rd Creating the Microprogram, con’t • R-type instruction microinstructions • Assigned states (addresses)6 and 7

14. for beq – do operand comparison (A - B) to produce Zero output on beq – load ALUOut into PC if Zero is true on j – load jump target addr into PC Creating the Microprogram, con’t • Branch (beq) and jump microinstructions • Assigned states (addresses)8 and 9

15. The Entire Control Microprogram

16. Microprogram to Microcode • A microassember is used to convert the mnemonic microprogram into the actual control signals (0’s and 1’) or microcode, for example

17. Microcode Implementation PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg Control PLA Outputs PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst AddrCtl 1 Microprogram Counter Adder System clock Addr select logic sequencing control Op5 Op4 Op3 Op2 Op1 Op0 Inst[31-26]

18. AddrCtl (sequencing control from microcode memory) dispatch table in PLA_2 to choose next instr 3 or 5 dispatch table in PLA_1 to choose next instr 2, 6, 8 or 9 Address Select Logic to control PLA 1 Microprogram Counter System Clock Adder 2 1 0 3 0 Dispatch PLA_2 Dispatch PLA_1 Addr select logic Op5 Op4 Op3 Op2 Op1 Op0 Inst[31-26]

19. Review: FSM Implementation PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg Combinational control logic PCSource Outputs ALUOp ALUSourceB ALUSourceA RegWrite RegDst Inputs Op5 Op4 Op3 Op2 Op1 Op0 Next State State Reg Inst[31-26] System Clock

20. Control Path Design Alternatives • Microprogram representation advantages • Easier to design, write, and debug Finite state diagram Initial representation Microprogram Microprogram counter + dispatch PLAs Sequencing control Explicit next state function Logic representation Logic equations Microcode Implementation technique Programmable Logic Array (PLA)