ENG241 Digital Design

1. ENG241 Digital Design Week #6 Sequential Circuits (Part A)

2. Week #6 Topics • Sequential Circuit Definitions • Latches • Flip-Flops • Delays in Sequential Circuits • Clock Gating ENG241/Digital Design

3. Resources • Chapter #6, Mano Sections • 6.1 Sequential Circuit Definition • 6.2 Latches • 6.3 Flip-Flops ENG241/Digital Design

4. Combinational Circuits vs. Sequential Circuits • Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer. • Combinational circuitscannot remember what happened in the past (i.e. outputs are a function of current inputs). • In certain cases we might need to store some info before we proceed with our computation or take action based on a certain state that happened in the past. • Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits. ENG241/Digital Design

5. Remembering States ENG241/Digital Design

6. Sequential Circuits • Information that is stored in the storage elements represent the state of the system. • The outputs will depend on the inputs and present state of the storage elements. Storage Elements ENG241/Digital Design

7. Types of Sequential Circuits • Two main types and their classification depends on the times at which their inputs are observed and their internal state changes. • Synchronous • State changes synchronized by one or more clocks • Asynchronous • Changes occur independently ENG241/Digital Design

8. Signal Examples Over Time Time Continuous in value & time Analog Digital Discrete in value & continuous in time Asynchronous Discrete in value & time Synchronous ENG241/Digital Design

9. Clocking of Synchronous Circuits • Changes enabled by clock ENG241/Digital Design

10. Comparison • Synchronous • Easier to analyze because can factor out gate delays • Speed of the system is determined by the clock (maybe slowed!) • Asynchronous • Potentially faster • Harder to analyze We will look mostly at synchronous ENG241/Digital Design

11. Basic Storage (How?) • Apply low or high for longer than tpd • But we are interested in storing information indefinitely! • Feedback will hold value • However we want inputs to our circuitry! ENG241/Digital Design

12. Latches • Are storage elements that can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states. • Latches are asynchronous circuits • Latches are used to build more complex synchronous circuits such as Flip Flops. ENG241/Digital Design

13. SR (set-reset) Latches: Asynchronous Storage Elements • Replace the inverters with NAND, NOR Gates • Basic storage made from gates • The information can be changed • S & R both 0 in “resting” state • Have to keep both from 1 at same time ENG241/Digital Design

14. Operation Set, Q=1 Undefined! Reset, Q=0 ENG241/Digital Design Keep State

15. Latch • Similar – made from NANDs • S & R both 1 in “resting” state • Have to keep both from 0 at same time ENG241/Digital Design

16. Add Control Input: SR Latch • An additional input determines when the state of the latch can be changed! • Can we avoid the undefined state? ENG241/Digital Design

17. D-type Latch • No illegal state ENG241/Digital Design

18. Transparency of Latches • The state of a latch is allowed to switch by a momentary change in value on the control input. • As long as C (the trigger ) is high, state can change! • This is called transparency What is wrong with transparency? ENG241/Digital Design

19. Effects of Transparency • Output of one latch may feedback • As soon as the input changes, shortly thereafter the corresponding output changes to match it. • The final state will depend on how long the clock pulse stays at level logic 1! (unreliable) • We need to predict the outputs at a certain moment in time! • Want to change latch state once • Depending on inputs at time of clock Storage Element Clock ENG241/Digital Design

20. Flip-Flops • Ensure only one transition • Two major types • Master-Slave (level triggered) • Two stage • Output not changed until clock disabled • Edge triggered • Change happens when clock level changes ENG241/Digital Design

21. Master-Slave SR Flip-Flop • When Master is enabled, Slave is disabled! • Output Q will not change when inputs change S C R S C R S C R SR Latch Master Slave ENG241/Digital Design

22. Timing Diagram • Trace the behavior • Note the illegal state • Is it transparent? 1 1 0 0 ENG241/Digital Design

23. Have We Fixed the Problem? • Output no longer transparent • Combinational circuit can use last values • New inputs appear at latches • Not sent to output until clock low • In one clock cycle we can predict what will happen • Note: Master-Slave = pulse triggered ENG241/Digital Design

24. JK Flip Flop • The JK Flip Flop is a modified version of the SR Flip Flop which eliminates the undesirable condition that leads to undefined outputs. • The JK flip flop performs three operations: • Set Q to 1 • reset Q to 0 • complement the output ENG241/Digital Design

25. Master-Slave JK Flip Flop The J inputsets the flip flop to 1. The K input resets the flip flop to 0. When both J and K are enabled, the output is complemented. ENG241/Digital Design

26. Edge-Triggered Flip-Flops • An Edge Triggered Flip-Flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal. • New state latched on clock transition • Low-to-high or high-to-low • Changes when clock high are ignored ENG241/Digital Design

27. Clock Responses We can classify Flip/Flops according to the response to the clock. ENG241/Digital Design

28. Edge Triggered D-Flip-Flop D C S C R ENG241/Digital Design

29. Characteristic Tables • Define the logical properties of a flip flop by describing its operations in tabular form. • They define the next state as a function of the inputs and the present state. • Q(t) refers to the present state prior to the application of a clock edge. • Q(t + 1) refers to the next state one clock period later. • Clock edges are not listed as inputs but are implied by the transition from t to t + 1. ENG241/Digital Design

30. D FF Characteristic Table The Characteristic Equation: Q(t + 1) = D(t) ENG241/Digital Design

31. Edge-Triggered D Flip Flop: Graphic Symbols • The triangle is called: dynamic indicator ENG241/Digital Design

32. Other Flip Flops • Other types of flip flops can be constructed by using the D flip flop and external logic. The two most commonly used are: • Edge triggered JK flip flops • T flip flops ENG241/Digital Design

33. JK Characteristic Table Characteristic Equation: Q(t+1) = J(t) Q’(t) + K’(t)Q(t) • Utilize the equation to create a JK flipflop from an existing D flipflop ENG241/Digital Design

34. Edge-Triggered JK Flip Flop Q(t+1) = J(t) Q’(t) + K’(t)Q(t) ENG241/Digital Design

35. Analysis of the JK Circuit • The circuit applied to the D input is D = JQ’ + K’Q • If J = 1 and K = 0, D = Q + Q’ = 1 (Set) • If J = 0 and K = 1, D = 0 (Reset) • If J = K = 0, D = Q, (No Change) • If J = K = 1, D = Q’ (Complement) ENG241/Digital Design

36. T T Flip Flop • The T Flip Flop is a complementing flip flop. • How can we obtain a T Flip Flop from a JK Flip Flop or D Flip Flop? Q(t+1) = TQ’(t) + T’Q(t) ENG241/Digital Design

37. T Flip Flop • TheT flip flopcan be obtained from a JK flip flop when inputs J and K are tied together. ENG241/Digital Design

38. Characteristic Equations • The D flip flop can be expressed as: • Q(t + 1) = D • The JK flip flop can be expressed as: • Q(t + 1) = JQ’ + K’Q • The T flip flop can be expressed as: • Q(t + 1) = TQ’ + T’Q • Characteristic Tables are used to • Derive the characteristic equations, • Analyze Sequential Circuits. ENG241/Digital Design

39. JK- Characteristic Equation JK 01 10 11 Q 00 0 1 Q(t+1) = J(t) Q’(t) + K’(t)Q(t) ENG241/Digital Design

40. Standard Symbols – Latches • Circle at input indicates negation ENG241/Digital Design

41. Symbols – Master-Slave • InvertedL indicates postponed output • Circle indicates whether enable is positive or negative ENG241/Digital Design

42. Symbols – Edge-Triggered • Arrow indicates edge trigger ENG241/Digital Design

43. Direct Inputs • Set/Reset independent of clock • Direct set or preset • Direct reset or clear • Often used for power-up reset ENG241/Digital Design

44. dataflow VHDL Design Styles VHDL Design Styles behavioral (algorithmic) structural Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Test benches ENG241/Digital Design

45. VHDL For Sequential Circuits • Several techniques have been discussed in class to describe the architecture of combinational logic circuits: • Data Flow • Structural • Statements used in “Data Flow” and “Structural” descriptions can be executed in parallel i.e. concurrently. • Another technique to describe the architecture of any circuit is to use Behavioral description. • The process statement is usually used to describe sequential designs. • The process statement consists of only sequential statements ENG241/Digital Design

46. VHDL For Sequential Circuits • To describe sequential circuits we usually use the “process” statement. • A process statement consists of • Sensitivity list  Process (CLK, RESET) This list enumerates exactly which signals causes the process statement to be executed. (Only events on these signals cause the process statement to be executed!) • Declarative region  Process (CLK, RESET) …… (declare local vars) Begin ….. END ENG241/Digital Design

47. VHDL for Positive Edge Triggered D-FF -- positive Edge-Triggered D flip-flop with reset -- VHDL Process Description library ieee; use ieee.std_logic_1164.all; entity dff is port (CLK, RESET, D : in std_logic; Q : out std_logic); end dff; architecture pet_pr of dff is begin process (CLK, RESET) begin if (RESET = `1’) then Q <= `0’; elsif (CLK’event and CLK = `1’) then - - you can use rising_edge(CLK) instead! Q <= D; end if; end process; end; ENG241/Digital Design

48. Flip-Flop Timing • Setup time (ts)– time that D must be available before clock edge • Hold time (th)– time that D must be stable after clock edge ENG241/Digital Design

49. Summary • Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer. • Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits. • Latches are storage elements that are asynchronous, transparent and are used to build more complex synchronous circuits such as Flip-Flops. • Flip-flops avoid the transparency problem faced by latches and are either Master-Slave pulse active or edge triggered. • Characteristic tables will be used to analyze the behavior of sequential circuits. ENG241/Digital Design

50. Extra Slides ENG241/Digital Design