Area- and Power-Reduced Standard-Cell Spanning Tree Adders

1. Pasquale Corsonello, University of Reggio Calabria Stefania Perri, University of Calabria Vitit Kantabutra, Idaho State University Area- and Power-Reduced Standard-Cell Spanning Tree Adders

2. Importance of Low-Power Adders • Adders are used in virtually all digital devices • Often more than one wide adder will appear in one device like a CPU • In CMOS, adders dissipate a lot of power because many transistors switch simultaneously

3. Adders in the Literature • Ripple adders • Low power, small, but slow • Carry-lookahead adders • Fast, high power, large • Carry-skip adders • A good compromise • Hybrid adders • Attain highest speed without as much area as carry-lookahead adders • Our new adder is a hybrid carry-lookahead/carry-skip adder

4. Our Previous Results -- Faster, Low-Cost Carry-Skip Adders Carry-skip adders are not usually as fast as carry-select or carry-look ahead adders, but are lower in cost. We invented a new type of fast carry skip adder. The new type of carry-skip adder can perform almost as well as traditional block carry-lookahead adders, but uses much less chip area and power.

5. 0 0 F F 1 1 S S Basic Carry-skip Adder Mux B Mux A 00100010 10110101 01110110 10110110 00011101 01001010 10001001 01001010 Block 3 Block 2 Block 1 Block 0

6. Our Adder • A 56-bit hybrid carry-lookahead, carry-skip adder • 56-bit is useful for IEEE double precision floating-point mantissa addition • Using carry-lookahead carry chain, generate carry-in signals for certain bit positions • Those carry-in signals are then fed into carry-skip adder blocks • If such a block is to be skipped, then the skipping is done very quickly with no rippling • If the block must spend time generating its own carry, then the carry chain’s delay is irrelevant • Thus the entire adder is always very fast

7. Carry-lookahead chain • Same as Kantabutra ’93 (IEEETC) • Uses mcc’s of various sizes for speed advantage • Balanced critical paths • Modified from Lynch-Swartzlander ’91 (ARITH), ’92 (IEEETC) • Used same mcc sizes

8. Top level architecture of new non-duplicated 16-bit module Note: Skip signals are active low

9. New m-bit block for the non-duplicated module(not least-, not most-significant block) Cin to entire 15 or 16-bit module Cin to this “small” block SkipIn chooses 1 of these 2 carry-in signals to become small-block carry-in signal

10. Least significant bit block

11. Performance summary

12. Chip photomicrograph