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14-bit 10MS

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14-bit 10MS

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    1. 14-bit 10MS/s Pipeline ADC EE 505 Final Project Designed by Sven Soell Kuang-Ming Yap

    2. Basic Architecture

    3. Our 14-bit ADC Architecture

    4. Details Power supply: 5 V Input Range : 1.75 V to 3.25 V (fully differential) Process: ami05 14 stages Each stage decodes 1.5 bit of information

    5. Residue Transfer Characteristic Vo,residue = 2Vi – Vref if Vi > Vref/4 d=2(10)2 2Vi if -Vref/4 <= Vi >= Vref/4 d=1(01)2 2Vi + Vref if Vi < -Vref/4 d=0(00)2

    6. Our 1.5 bit Stage Architecture Single ended, Implemented fully differential

    7. Sub Devices Comparator Switched Capacitor Feedback Circuit Digital-to-Analog Converter Amplifier

    8. Comparator

    9. Comparator Minimum size nmos (differential input pair).

    10. Switch Capacitor Feedback Circuit Feedback Capacitor is 2 x 3pF Sized according to kt/C noise

    11. Digital to Analog Converter Digital logic with an analog MUX Digital logic is implemented in verilog

    12. Operational Amplifier Single-stage fully complementary gain boosted folded cascode amplifier. DC gain > 110dB UGF > 450 MHz with 5pF load Phase Margin > 50 degrees at unity gain. Power Consumption > 35mW

    13. Operational Amplifier

    14. Operational Amplifier

    15. Clocking Implemented in Verilog

    16. Clocking

    17. Resistor String

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