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Supplementary notes for pipelining

Supplementary notes for pipelining. LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____ ADD ____,____,____ Prepared by: Cem Erg ün. LW. before<1>. before<2>. before<3>. before<4>. ADD. PC. Clock Cycle 1.

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Supplementary notes for pipelining

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  1. Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____; assume that, condition for branch is not satisfied OR ____,____,____ ADD ____,____,____ Prepared by: Cem Ergün

  2. LW before<1> before<2> before<3> before<4> ADD PC Clock Cycle 1 PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  3. SUB LW before<1> before<2> before<3> ADD PC Clock Cycle 2 PCSrc ID/EX EX/MEM MEM/WB WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  4. BEQ SUB LW before<1> before<2> ADD ADD PC 0 MUX 1 Clock Cycle 3 PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] RegDst I[20-16] ALUOp I[15-11]

  5. OR BEQ SUB LW before<1> ADD ADD PC 0 MUX 1 Clock Cycle 4 PCSrc EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] ALUOp I[15-11]

  6. ADD OR BEQ SUB LW ADD ADD PC 1 MUX 0 Clock Cycle 5 PCSrc EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY ADDRESS READ DATA RESULT MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] 0 ALUOp MUX I[15-11] 1

  7. after<1> ADD OR BEQ SUB ADD ADD PC 1 MUX 0 0 MUX 1 Clock Cycle 6 PCSrc EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY ADDRESS READ DATA RESULT MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] ALUOp I[15-11]

  8. after<2> after<1> ADD OR BEQ ADD ADD PC 0 MUX 1 Clock Cycle 7 EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] ALUOp I[15-11]

  9. after<3> after<2> after<1> ADD OR ADD ADD PC 1 MUX 0 Clock Cycle 8 EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] 0 ALUOp MUX I[15-11] 1

  10. after<4> after<3> after<2> after<1> ADD ADD ADD PC 1 MUX 0 Clock Cycle 9 EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] 0 ALUOp MUX I[15-11] 1

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