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Automatic Instruction Scheduler Retargeting by Reverse-Engineering

Automatic Instruction Scheduler Retargeting by Reverse-Engineering. Matthew J. Bridges , Neil Vachharajani, Guilherme Ottoni, David I. August Liberty Research Group Department of Computer Science Princeton University. Static Schedule. Add. Shl. Sub. Xor. Dynamic Schedule. Add. Shl.

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Automatic Instruction Scheduler Retargeting by Reverse-Engineering

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  1. Automatic Instruction Scheduler Retargeting by Reverse-Engineering Matthew J. Bridges, Neil Vachharajani, Guilherme Ottoni, David I. August Liberty Research Group Department of Computer Science Princeton University

  2. Static Schedule Add Shl Sub Xor Dynamic Schedule Add Shl Sub Resource Usage Xor ALU0 Add ALU0 Shl ALU1 Sub Xor ALU1 Structural Hazards Code Resources Add ALU0 ALU1 Time Shl ALU0 ALU1 Sub ALU0 ALU1 Xor

  3. Static Schedule Dynamic Schedule Add Add Sub Sub Shl Shl Xor Xor Resource Usage ALU0 Add ALU0 Shl ALU1 Sub Xor ALU1 Structural Hazards Code Resources Add ALU0 ALU1 Shl Time ALU0 ALU1 Sub ALU0 ALU1 Xor

  4. Encoding Structural Hazards Processor Manuals Pros: • Easily Available • Standard Methodology Cons: • Processor manual does not describe the actual machine • Takes several man-weeks to translate processor manual into machine description • Machine description written incorrectly Processor Manuals Offline Compiler Machine Description Hazard Detector Scheduler

  5. Processor Manuals IA64 Instructions Set Reference Vol. 3 ~370 pages of ISA description Itanium 2 Processor Reference Manual~200 pages of microarchitecural details

  6. Humans aren’t Perfect IMPACT Itanium 2 Machine Description OP_SHIFT (alt(ALT_SHIFT_REG)); OP_SHIFT (alt||(ALT_SHIFT_IMM)); ALT_SHIFT_REG (format (OF_IREG_IREG resv(RL_Itype)); ALT_SHIFT_IMM (format (OF_IREG_IMM6 resv(RL_Itype)); Itanium Instruction Set Reference Vol. 3: Page 3:212 Itanium 2 Processor Reference Manual: Page 27

  7. Encoding Structural Hazards Architecture Description Language[LISA][nML] Pros: • Machine description accurately describes processor Cons: • ADLs are limited • Not used for general purpose processors • Often unavailable ADL Offline Compiler Machine Description Hazard Detector Scheduler

  8. Encoding Structural Hazards Query machine while scheduling [Baker `91][Dupre `04] Pros: • Avoids human errors • Easily available Cons: • Increase in compile time • Unable to cross-compile Hazard Detector Scheduler Compiler

  9. Encoding Structural Hazards Query machine a priori Pros: • Avoids human errors • Easily available • Avoid scheduling overhead Cons: • ? Hazard Detector Scheduler Machine Description Compiler Offline Structural HazardDetermination Algo.

  10. Limits of Querying Goal: Perfectly characterize the machine Goal: Characterize the machine Machine A Machine B Finite Finite Infinite Infinite

  11. Width (w) I I I I I I I I I I I I Myopia Millennia Depth (p) Pipelined 230 Millennia No Order 3 Millennia Instructions (I) Categorization 1.3 Hours Width (w) Width (w) Width (w) Width (w) Instructions (I) Categories (C) Instructions (I) Instructions (I) Identifying a Subspace to Explore # Possible Instruction Schedules Assumption General Itanium 2 Time 100 Schedules/Second

  12. Cost of Assumptions

  13. 2. Split Categories • Perform a Random Walk • Longer walk = more accurate categories 3. Extract Canonical Instructions 4. Exhaustive Exploration of Canonical Instructions … 5. Update machine description Reverse-Engineering Algorithm 1. All Instructions in a Single Category

  14. Cost of Finding Categories

  15. Conclusion • Obtaining structural hazards for use in instruction scheduling is error prone • Processors manuals wrong or confusing • Manual translation is error prone • ADLs aren’t available • We can automatically extract structural hazards useful for scheduling • It is impossible to determine all structural hazards a priori • It is possible to find sufficient hazard information to produce good schedules • Algorithm achieves 81-100% of manual resource map performance • Greatly reduces the time needed to retarget the instruction scheduler of a compiler • Facilitates Design Space Exploration

  16. Thank You

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