Substrate noise reduction in mixed-signal ICs

1. Substrate noise reductionin mixed-signal ICs BWRC seminar 09/25/2009 Mark Vesterbacka Link�ping University, Sweden markv@isy.liu.se

3. Introduction Evolution of ICs Complete systems integrated on samedie reduce power, size, and cost Processing in digital, analog, and RFdomains Substrate noise is a growing challenge Switching noise is an order of magnitudelarger than device noise Switching noise is spread by substrate Performance of analog and RF circuits is degraded by noise Problem grows with more switching and shorter distance

4. Introduction We need techniques to reduce substrate noise, e.g. Separation of noisy and sensitive circuits Substrate modeling Careful design of power supply Reduction of simultaneous switching Turn off unused functions Introduce special circuits etc.

5. Switching noise Power supply parasitics L in nH�s, R in ?�s Ex: supply noise Inverter chain in0.13 �m SOI CMOS On-chip measurementusing comparator andDAC

6. Switching noise Switching on-chip load Only Ipower contributes to switching noise Oscillations on on-chip supply lines are antisymmetrical

7. Switching noise Switching off-chip load Data-dependent current path for single-ended output

8. Substrate coupling Injection of switching noise Noise injection through substrate contacts dominates Signals are capacitively coupled to substrate through pn junctions and interconnect

9. Substrate coupling Accurate substrate modeling requires 3D analysis Ex: two 50 �m-by-50 �m surfaces 50 �m apart

10. Substrate coupling Results using FEMLAB

11. Noise reception Reception mechanisms Direct coupling via substrate contacts Capacitive coupling to passive components and interconnect Body effect, resulting in fluctuating drain current Effects on analog circuits Differential noise affects signal directly Common mode noise isintermodulated with signal SNR, SFDR, DR, etc. areimpaired

12. Noise reception Ex: filter chip 0.35 �m CMOS 630 FAs + 350 DFFs 10 two-stage OPAs p- bulk

13. Noise reduction Use different supply wires for digital, IO, guard bands, analog

14. Noise reduction Multiple supply wires reduce L Useful for improving bothdigital and analog L Mutual L affects effective L

15. Noise reduction Single bonding vs double bonding Double bonding decreases R, but not L More useful for high frequency due to skin effect Similar option is to use a thick bond wire Use low-Z package Expensive

16. Noise reduction Add on-chip decoupling C May require dampening R due to lower resonance f Add series RLC circuit can counteract main resonance peak Typically requires off-chip components Proper driver design Prefer long rise and fall times Avoid simultaneous switching

17. Noise reduction Use special logic circuits with low di/dt Examples:

18. Noise reduction Physical distance and guard bands are useful in p- bulk Noise tends to be uniform in p+ bulk Inefficient when dist > 4�epi_thickness

19. Noise reduction SOI vs bulk coupling,with/without guard Ex: 2 x 2 mm2 chip 2 x 0.9 mm2 areasseparated 0.2 mm 2 x 0.1 mm2 guardband in middle

20. Noise reduction in f domain Design digital circuits with periodic supply current ? Frequency content of switching noise is located above clock f Method requires symmetric circuit implementation Differential RZ signaling reduces datadependency of supply current

21. Noise reduction in f domain Test chip 0.13 �m CMOS p+ bulk New and reference pipelined 16-bit RCA on same chip

22. Noise reduction in f domain Results Peak PSD �8.5 dB/Hz Max f +20% Area +35% Power +200%

23. Noise reduction in f domain Comments Proof of concept � layout symmetry and test pattern was imperfect Should be good also for cryptography Research on 2nd generation circuits Improve pipeline concept � single latch replaces master-slave DFF Investigate symmetrical circuit design with respect to mismatch Characterize high frequency properties Investigate symmetrical layout Resolve conflict in receiving latch stage Merge logic into receiving latch stage Design circuits with same throughput improves noise and relative P

24. Conclusion We discussed Switching draws a large current peak from the power supply Oscillation is triggered in the power supply net due to L and C Noise is spread through the substrate, mainly via bias contacts Substrate noise is reduced by proper design of power supply,guard bands, and floorplanning Less switching noise is generated with special circuit design We showed A new method to reduce digital switching noise up to clock f

25. References Erik Backenius, Reduction of Substrate Noise in Mixed-Signal Circuits, Link�ping Studies in Science and Technology, Dissertations, no. 1094, 2007. A. Afzali-Kusha, M. Nagata, N.K. Verghese, and D.J. Allstot, �Substrate noise coupling in SoC design: Modeling, avoidance, and validation,� Proc. IEEE, vol. 94, no. 12, pp. 2109-2138, Dec. 2006. X. Aragon�s, J. L. Gonz�lez, and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Academic Publishers, 1999. S. Donnay and G. Gielen, Substrate Noise Coupling in Mixed-Signal ASICs, Kluwer Academic Publishers, 2003. S.M.Y. Sherazi, S. Asif, E. Backenius, and M. Vesterbacka, �Reduction of substrate noise in sub clock frequency range,� IEEE Trans. Circ. Syst. I, accepted 2009.