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Design of a 300 Mbps Unified 3G/4G Turbo Decoder Using High-Level Synthesis. Primary Author: Sandeep RK Secondary Author: Pankaj Saxena Company/Organization: Broadcom. Agenda. Motivation Turbo Decoder Challenges Methodology Results HLS Advantages Recommendations. Motivation.
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Design of a 300 Mbps Unified 3G/4G Turbo Decoder Using High-Level Synthesis Primary Author: Sandeep RK Secondary Author: Pankaj Saxena Company/Organization: Broadcom
Agenda • Motivation • Turbo Decoder • Challenges • Methodology • Results • HLS Advantages • Recommendations
Motivation • Scalable architecture • Should support the following throughputs: • 3G – 3.6, 7.2, 14, 21, 42, 84, 168 Mbps • LTE – 75, 100, 150, 300 Mbps • Minimum area and power • Establish high-level synthesis (HLS) flow
3G/LTE Turbo Encoder • Ref: 3GPP TS 36.212 version 10.2.0 Release 10
Challenges • Address conflicts in 3G interleaver • >5000 block sizes in 3G. • Results in nondeterministic throughput. • Modeling is required to choose the architecture. • Odd block sizes in 3G • Interleaved address generation in 3G
Turbo Decoder • 300 Mbps for LTE, and 168 Mbps for 3G • Eight parallel Radix4 MAP decoders • Up to eight full iterations • CRC-based early termination
Methodology • Design and test bench: SystemC • Each block in one or two CThreads • Verification: Bit matching with reference vectors • HLS tool: Forte Cynthesizer • RTL synthesis: Design Compiler • Single test bench for performance evaluation, RTL, and netlist simulations
Results • ~60% area reduction compared to separate 3G & 4G decoders. • Area is reduced by 10% due to HLS. • ~50% is memory. • Area is reduced proportional to throughput due to scalable architecture. • BER remains the same. • Throughput requirements are met for both 3G & LTE.
HLS Advantages • Architecture exploration • Process technology independent design • Readily available interfaces • Built-in math operations like saturation, rounding, etc. • Smaller area • Easy to work with memories • Shorter design cycle
Recommendations • Control signals should flow along with the data path. • Adds flexibility to synthesize designs at different frequencies. • Reset values to all variables. • SystemC assigns 0 by default. • Group the inputs/outputs having the same delay requirements. • Avoid multicycle paths. • Use consistent coding style. • Input registering versus output registering.
Recommendations (continued) • Memory access delays are different in SystemC and RTL. Need a scheme to avoid SystemC/RTL mismatch. • Avoid write-through conditions in dual-port memories. • Be careful about simultaneous read/write operations in single-port memories.
