Electronics and Data Acquisition

1. Electronics and Data Acquisition D. Casper (Irvine) with P. Rubinov (Fermilab) D. Naples and V. Paolone (Pittsburgh)

2. Outline • Overview • Responsibilities • Physics Requirements • Technical Review • Safety Issues • Costs • R&D Status and Plans Electronics and DAQ

3. Electronics in MINERA • Front-end Electronics • High-voltage for MAPMTs • Digitization • One board on each PMT box • DAQ and Slow Control • Front-end/computer interface • Distribute trigger and synchronization • Three VME crates + server • Power and Rack Protection • 7 kW required (includes MAPMTs) • 48 V supplies, fanouts and interlock provided by Fermilab • See D. Harris talk Electronics and DAQ

4. Front-End Responsibilities • Front-end Digitizer Boards • One board per MAPMT (64 channels), mounted outside PMT box • Programmable Cockroft/Walton HV supply, on removable daughter card • Discriminators • Analog pipeline • High- and low-gain QDC’s • TDC logic • LVDS interface to DAQ system • Design, Prototyping and Firmware • Fermilab (Rubinov) andPittsburgh (Naples, Paolone) • Production, Testing and Installation • Pittsburgh Simplified schematic of front-end board Electronics and DAQ

5. DAQ Responsibilities • Key Component: Chain Read-Out Controller (CROC) • Each serves 4 chains of 12 front-end boards (48 × 64 = 3072 channels/ board) • Distribute synchronization signals from NuMI/MINOS • Pull data from front-end after spill • Pass configuration, HV control messages between DAQ computer and front-end • LVDS Chains • Support token-ring communication between CROC’s and front-end • VME Interface and Electronics • Two crates for CROCs, one for miscellaneous logic and monitoring • PCI/VME bridge • DAQ Computer • Design, Prototyping and Firmware • Fermilab (Rubinov) and Irvine (Casper) • Production, Testing and Software • Irvine Electronics and DAQ

6. Front-end Physics Requirements • Precision Coordinate Resolution and Tracking • Relies on charge-sharing between neighboring strips • Requires low-noise, single-PE sensitivity • Calorimetry, dE/dx and Particle Identification • Relies on specific ionization measurement • Requires large dynamic range (50  minimum ionizing) • High- and low-gain ADC channels for each pixel • Strange Particle, Muon Decay ID • Relies on timing • Requires few-ns time resolution on front-end, global synchronization • TDC functionality implemented in firmware • Pattern Recognition for Exclusive Reconstruction of Complex Topologies • Timing and 4-hit buffers/channel allow separation of multiple interactions in spill • Not multiplexed Electronics and DAQ

7. DAQ Physics Requirements • Modest Data Rate • Expect about 1 event per spill • Low occupancy per event • Two-second window to read digitizers before next spill arrives • Unbiased Trigger • Gate can be opened in advance of beam arrival (unbiased trigger) • No need for complicated trigger logic based on PMT signals • Collect cosmic rays with random gates (or something more sophisticated) • Global Synchronization • Requires high-bandwidth connection to front-end boards • LVDS chain Electronics and DAQ

8. High-Voltage • Cockroft-Walton power supply for MAPMT on daughter-card outside the PMT boxes • Allows easy maintenance and replacement without breaking light seal • Expected HV range: 700 – 800 V • Voltage under computer control and monitoring over LVDS chain • Controller based on Fermilab RMCC chip being developed for BTeV Electronics and DAQ

9. Charge Discrimination and Digitization • Charge digitization scheme is based on the TRiP chip developed by DØ • 16 discriminator channels/chip • 32 analog pipeline channels/chip • Up to four hits/channel/spill • Four chips per front-end board • Input signal for each pixel is passively divided into high- and low-gain ADC channels • Maintain single PE performance for charge-sharing • Increase dynamic range by ten for dE/dx measurement • 12-bit digitization Electronics and DAQ

10. Timing and Firmware • Each pixel’s discriminator latch is used to measure the time of the pulse • Important to separate multiple interaction in spill, identify delayed coincidence from strange particles • 25 MHz Tevatron reference clock is multiplied by 4 in a Phase-Locked Loop, then phase-shifted by 90 degrees to give a “quadrature” clock with2.5 ns resolution least-count. • A reprogrammable logic array controls the sequencing of timing and charge read-out, driven by a local oscillator • Digitized times and charges stored in onboard RAM for readout after spill Electronics and DAQ

11. LVDS Chains • All signals to and from front-end carried by LVDS rings • 12 front-end boards per chain • Transmit + Receive ports on each front-end board • Token ring protocol • Functionality • Read/write digital data in front-end memory • Open gate for spill in response to NuMI timing • Synchronization (1.5 – 2 ns jitter for 12-board ring) • Control and monitor HV • Reprogram FPGA firmware Electronics and DAQ

12. CROC Modules and VME • 11 Chain Read-out Controllers, each controlling 4 LVDS rings • Two VME crates • Spill timing from NuMI using MINOS modules • Commercial VME hardware to measure spill timing, generate artificial triggers, etc. in third VME crate • Commercial PCI/VME interface to DAQ computer • Rack-mounted dual-CPU server for data acquisition and storage Electronics and DAQ

13. Safety Issues • Cables • LVDS cables will be halogen-free CAT-5e network cable • To be approved by Fermilab ES&H • Rack and electronics protection • Fuses on front-end board and power fanouts • A system to monitor hazards in the hall and automatically shut off power to the front-end electronics and DAQ (in the event of fire, flood, etc) will be provided by Fermilab • Cavern egress and installation • See installation talk by D. Harris Electronics and DAQ

14. Prototyping • 16-channel front-end prototype successfully tested in Summer 2004 with invaluable Fermilab support • All charge and time digitization performance requirements satisfied or exceeded • LVDS interface and jitter tested with four front-end prototypes at FNAL, December 2004 • Second-generation front-end board, with 64 channels and HV supply to be completed and tested by Q3 2005 • CROC prototype to be completed and tested by Q4 2005 Electronics and DAQ

15. Front-end Costs • Total Pittsburgh direct costs for front-end electronics: $453,293 • Fabricate 580 front-end boards (includes 15% spares): $351,480 ($606/board - $150 PC board, $336 components, $120 assembly) • Produce 2,500 TRiP chips: $70,000 • TRiP tester board: $15,000 • Front-end test set-up: $9,408 • Undergraduate labor: $7,405 • Total cost per detector channel: $14.62 • Includes 40-50% contingency • Fermilab contributions to front-end electronics: $202,500(+) • Design, Prototyping, Firmware (17.4 months Elec. Engineer): $195,000 • M&S for prototype: $7,500 • (+) 160 hours technician labor for prototype assembly Electronics and DAQ

16. DAQ Costs • Total Irvine direct costs for DAQ: $209,874 • VME crates and interface: $66,000 • Fabricate 16 CROC VME modules: $48,000 ($3,000 per board) • Commercial VME modules (TDC, pulser, etc): $20,000 • NuMI/MINOS timing modules: $18,000 • DAQ computer and software: $18,000 • LVDS cables: $15,750 • Prototyping and test hardware: $13,000 • Undergraduate labor: $11,124 • Total cost per detector channel: $6.78 • Includes 40% contingency on CROC, 20% on commercial items • Fermilab contributions: $133,500 • 1 year EE (design, prototyping and firmware): $130,000 • $3,500 M&S for prototype Electronics and DAQ

17. Schedule and Milestones End 2006Electronics Complete Electronics and DAQ

18. Summary • Electronics/DAQ design already well-advanced • Overall cost: $21.40/channel, including EDIA, spares + contingency • Strongly leverages existing technology wherever possible • Most important technical risks already addressed • TRiP digitization/buffering scheme • Timing • LVDS interface • Plan for final design completed and tested in about 12 months • Production and check-out complete in about 24 months • Final boards to be used for PMT testing • About six months prior to detector installation Electronics and DAQ